DP8303A

更新时间： 2024-02-10 11:05:52

品牌	Logo	应用领域
美国国家半导体 - NSC		/
页数	文件大小	规格书
6页	108K
描述
8-Bit TRI-STATE-R Bidirectional Transceiver (Inverting)

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技术参数
数据手册

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DP8303A 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.92
Is Samacsys：	N	控制类型：	COMMON CONTROL
计数方向：	BIDIRECTIONAL	JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e0	位数：	8
功能数量：	1	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	输出极性：	INVERTED
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
子类别：	Bus Driver/Transceivers	标称供电电压 (Vsup)：	5 V
表面贴装：	NO	技术：	TTL
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	翻译：	N/A
Base Number Matches：	1

DP8303A 数据手册

February 1996

DP8303A 8-Bit TRI-STATE

Bidirectional Transceiver (Inverting)

General Description

Features

8-bit directional data flow reduces system package

count

This family of high speed Schottky 8-bit TRI-STATE bidirec-

tional transceivers are designed to provide bidirectional

drive for bus oriented microprocessor and digital communi-

cations systems. They are all capable of sinking 16 mA on

the A ports and 48 mA on the B ports (bus ports). PNP

inputs for low input current and an increased output high

Bidirectional TRI-STATE inputs/outputs interface with

bus oriented systems

PNP inputs reduce input loading

Output high voltage interfaces with TTL, MOS, and

CMOS

(V ) level allow compatibility with MOS, CMOS, and other

technologies that have a higher threshold and less drive

capabilities. In addition, they all feature glitch-free power

up/down on the B port preventing erroneous glitches on the

system bus in power up or down.

48 mA/300 pF bus drive capability

Pinouts simplify system interconnections

Transmit/Receive and chip disable simplify control logic

Compact 20-pin dual-in-line package

Bus port glitch free power up/down

DP8303A and DP7304B/DP8304B are featured with Trans-

mit/Receive (T/R) and Chip Disable (CD) inputs to simplify

control logic. For greater design flexibility, DP8307A and

DP7308/DP8308 are featured with Transmit (T) and

Receive (R) control inputs.

Logic and Connection Diagrams

Dual-In-Line Package

TL/F/5856–1

TL/F/5856–2

Top View

Order Number DP8303AN

See NS Package Number N20A

Logic Table

Inputs

Resulting Conditions

Chip Disable

Transmit/Receive

A Port

OUT

B Port

OUT

TRI-STATE

Don’t care

TRI-STATEÉ is a registered trademark of National Semiconductor Corp.

1996 National Semiconductor Corporation

TL/F/5856

RRD-B30M36/Printed in U. S. A.

http://www.national.com

12 3 4 5 6

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