Datasheet > DP8051CPU_03

DP8051CPU_03

更新时间： 2024-10-14 03:30:15

品牌	Logo	应用领域
DCD		微控制器
页数	文件大小	规格书
9页	130K
描述
Pipelined High Performance 8-bit Microcontroller ver 3.10

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DP8051CPU_03 数据手册

DP8051CPU

Pipelined High Performance

8-bit Microcontroller

ver 3.10

O V E R V I E W

C P U F E A T U R E S

DP8051CPU is an ultra high perform-

ance, speed optimized soft core of a single-

chip 8-bit embedded controller dedicated for

operation with fast (typically on-chip) and slow

(off-chip) memories. The core has been de-

signed with a special concern about perform-

ance to power consumption ratio. This ratio

is extended by an advanced power manage-

ment unit PMU.

● 100% software compatible with industry

standard 8051

● Pipelined RISC architecture enables to

execute instructions 10 times faster com-

pared to standard 8051

● 24 times faster multiplication

● 12 times faster addition

● Up to 256 bytes of internal (on-chip) Data

DP8051CPU soft core is 100% binary-

compatible with the industry standard 8051 8-

bit microcontroller. There are two configura-

tions of DP8051CPU: Harward where internal

data and program buses are separated, and

von Neumann with common program and ex-

ternal data bus. DP8051CPU has Pipelined

RISC architecture 10 times faster compared

to standard architecture and executes 85-200

million instructions per second. This per-

formance can also be exploited to great advan-

tage in low power applications where the core

can be clocked over ten times more slowly

than the original implementation for no per-

formance penalty.

Memory

● Up to 64K bytes of internal (on-chip) or

external (off-chip) Program Memory

● Up to 16M bytes of external (off-chip) Data

Memory

● User programmable Program Memory Wait

States solution for wide range of memories

speed

● User programmable External Data Memory

Wait States solution for wide range of

memories speed

● De-multiplexed Address/Data bus to allow

DP8051CPU is delivered with fully auto-

mated testbench and complete set of tests

allowing easy package validation at each stage

of SoC design flow.

easy connection to memory

● Dedicated signal for Program Memory

writes.

● Interface for additional Special Function

Registers

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

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