Datasheet > DNC5X3125

DNC5X3125

更新时间： 2024-09-23 22:19:03

品牌	Logo	应用领域
杰尔 - AGERE		以太网
页数	文件大小	规格书
18页	262K
描述
Gigabit Ethernet Transceiver Macrocell

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DNC5X3125 数据手册

Advance Data Sheet

March 2000

DNC5X3125

Gigabit Ethernet Transceiver Macrocell

Overview

Features

The DNC5X3125 is a low-cost, low-power transceiver

macrocell. It is used for data transmission over fiber

or coaxial media in conformance with IEEE* 802.3z

Gigabit Ethernet specification and Fibre Channel

ANSI^†X3T11 at 1.0 Gbits/s and 1.25 Gbits/s.

■ Designed to operate in Ethernet, fibre channel,

FireWire^‡or backplane applications.

■ Operationally compliant to IEEE 802.3z Gigabit

Ethernet specification.

■

Operationally compliant to Fibre Channel ANSI

The transmitter section accepts parallel 10-bit

8b/10b encoded data that is latched on the rising

edge of TBC. It also accepts the low-speed, TTL

compatible system clock, REFCLK, and uses this

clock to synthesize the internal high-speed serial bit

clock. The serialized data is then available at the dif-

ferential PECL outputs, terminated in 50 Ω or 75 Ω to

drive either an optical transmitter or coaxial media.

Gbits/s—

X3T11. Provides FC-0 services at 1.0

1.25 Gbits/s (10-bit encoded data rate).

■

—

100 MHz 125 MHz differential or single-ended

reference clock.

■ 10-bit parallel interface.

■ 8b/10b encoded data.

The receive section receives high-speed serial data

at its differential PECL input port. This data is fed to

the digital clock recovery section, which generates a

recovered clock and retimes the data. The retimed

data is deserialized and presented as 10-bit parallel

data on the output port. A divided-down version of

the recovered clock, synchronous with parallel data

bytes, is also available as a TTL compatible output.

The receive section recognizes the comma character

and aligns the comma-containing byte on the word

boundary, when ENCDET = 1.

■

High-speed comma character recognition (K28.1,

K28.5, K28.7) for latency-sensitive applications

and alignment to word boundary.

■

—

Two 50.0 MHz 62.5 MHz receive-byte clocks.

Single analog PLL design requires no external

components for the frequency synthesizer.

■

Novel digital data lock in receiver avoids the need

for multiple analog PLLs.

■

Expandable beyond single-channel SERDES.

PECL high-speed interface I/O for use with optical

transceiver or coaxial copper media.

■ Requires one external resistor for PECL output ref-

erence level definition.

■

Low-power digital 0.25 m CMOS technology.

3.3 V ± 5% power supply.

■ 0 °C—

70 C ambient temperature.

* IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

† ANSI is a registered trademark of American National Standards

Institute.

‡ FireWire is a registered trademark of Apple Computer, Inc.

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DNC-63-40-PPV-A	FESTO	获取价格	ISO cylinder
DNC-63-500-PPV	FESTO	获取价格	ISO cylinder
DNC-63-500-PPV-A	FESTO	获取价格	ISO cylinder
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DNCE	HAMMOND	获取价格	PANNEAUY POUR BATI AVEC ENTREE DE CABLE
DNCE19	HAMMOND	获取价格	MOUNTING HARDWARE NOT INCLUDED
DNCE19BK1	HAMMOND	获取价格	MOUNTING HARDWARE NOT INCLUDED

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