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DMMT5551S PDF预览

DMMT5551S

更新时间: 2024-09-29 21:53:59
品牌 Logo 应用领域
美台 - DIODES 晶体晶体管
页数 文件大小 规格书
3页 74K
描述
MATCHED NPN SMALL SIGNAL SURFACE MOUNT TRANSISTOR

DMMT5551S 数据手册

 浏览型号DMMT5551S的Datasheet PDF文件第2页浏览型号DMMT5551S的Datasheet PDF文件第3页 
SPICE MODEL: DMMT5551  
DMMT5551/DMMT5551S  
MATCHED NPN SMALL SIGNAL SURFACE MOUNT  
TRANSISTOR  
Features  
·
·
·
·
·
·
·
Epitaxial Planar Die Construction  
A
Complementary PNP Type Available (DMMT5401)  
Ideal for Medium Power Amplification and Switching  
Intrinsically Matched NPN Pair (Note 1)  
SOT-26  
C
B
Dim Min Max Typ  
2% Matched Tolerance, hFE, VCE(SAT), VBE(SAT)  
1% Matched Tolerance, Available (Note 2)  
A
B
C
D
F
0.35 0.50 0.38  
1.50 1.70 1.60  
2.70 3.00 2.80  
Available in Lead Free/RoHS Compliant Version (Note 5)  
H
¾
¾
¾
¾
0.95  
0.55  
K
J
M
Mechanical Data  
H
J
2.90 3.10 3.00  
0.013 0.10 0.05  
1.00 1.30 1.10  
0.35 0.55 0.40  
0.10 0.20 0.15  
·
·
Case: SOT-26  
F
L
D
Case Material: Molded Plastic. UL Flammability  
Classification Rating 94V-0  
K
L
·
·
·
·
Moisture Sensitivity: Level 1 per J-STD-020C  
Terminal Connections: See Diagram  
M
a
E2  
C2  
E1  
E1  
C2  
C1  
Terminals: Solderable per MIL-STD-202, Method 208  
0°  
8°  
¾
Also Available in Lead Free Plating (Matte Tin Finish  
annealed over Copper leadframe). Please see Ordering  
Information, Note 9, on Page 2  
All Dimensions in mm  
B1  
E2  
B2  
C1  
B1  
B2  
·
·
·
Marking (See Page 2): K4R & K4T  
Ordering & Date Code Information: See Page 2  
Weight: 0.006 grams (approx.)  
DMMT5551S  
(K4T Marking Code)  
DMMT5551  
(K4R Marking Code)  
@ TA = 25°C unless otherwise specified  
Characteristic  
Maximum Ratings  
Symbol  
VCBO  
VCEO  
VEBO  
IC  
Value  
180  
Unit  
V
Collector-Base Voltage  
Collector-Emitter Voltage  
160  
V
Emitter-Base Voltage  
6.0  
V
Collector Current - Continuous (Note 3)  
Power Dissipation (Note 3, 4)  
200  
mA  
mW  
K/W  
°C  
Pd  
300  
RqJA  
Thermal Resistance, Junction to Ambient (Note 3)  
Operating and Storage and Temperature Range  
417  
Tj, TSTG  
-55 to +150  
Notes: 1. Built with adjacent die from a single wafer.  
2. Contact the Diodes, Inc. Sales department.  
3. Device mounted on FR-4 PCB, 1 inch x 0.85 inch x 0.062 inch; pad layout as shown on Diodes Inc. suggested pad layout  
document AP02001, which can be found on our website at http://www.diodes.com/datasheets/ap02001.pdf.  
4. Maximum combined dissipation.  
5. No purposefully added lead.  
DS30436 Rev. 4 - 2  
1 of 3  
DMMT5551/DMMT5551S  
www.diodes.com  
ã Diodes Incorporated  

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