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DMAC

更新时间： 2024-11-24 03:30:03

品牌	Logo	应用领域
DCD		控制器
页数	文件大小	规格书
4页	124K
描述
Media Access Controller

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中文翻译

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数据手册

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DMAC 数据手册

DMAC

Media Access Controller

ver 2.07

● Supports full and half duplex operation at

O V E R V I E W

10 Mbps or 100 Mbps

The DMAC is hardware implementation of

media access control protocol defined by the

IEEE standard. DMAC in cooperation with

external PHY device enables network func-

tionality in design. It is capable of transmitting

and receiving Ethernet frames to and from

the network. Half and full duplex modes are

supported, as well 10 and 100 Mbit/s speed.

The core is able to work with wide range of

processors: 8, 16 and 32 bit data bus, with

little or big endian byte order format. Design

is technology independent and thus can be

implemented in variety of process technolo-

gies. This core strictly conforms to IEEE

802.3 standard.

● CRC-32 algorithm calculates the FCS

nibble at a time, automatic FCS genera-

tion and checking, able to capture frames

with CRC errors if required

● Lite design, small gate count and fast

operation

● Programmable or fixed MAC address

● Promiscuous mode support

● Dynamic PHY configuration by MII man-

agement interface

● Receive FIFO able to store many mes-

sages at a time

● Allows operation from a wide range of

input bus clock frequencies

K E Y F E A T U R E S

● Conforms to IEEE 802.3-2002 specifica-

● Fully synthesizable

● Static synchronous design with positive

tion

edge clocking and synchronous reset

● 8/16/32-bit CPU slave interface with little

● No internal tri-states

● Scan test ready

or big endianess

● Simple interface allows easy connection

to CPU

A P P L I C A T I O N S

● Embedded microprocessor boards

● Narrow address bus with indirect I/O in-

terface to the transmit and receive data

dual port memories

● Networking devices (Network Interface

Cards, routers, switches)

● Supports 10BASE-T and 100BASE-

TX/FX IEEE 802.3 compliant MII PHYs

● Communications systems

● Media Independent Interface (MII) for

connection to external 10/100 Mbps PHY

transceivers

All trademarks mentioned in this document

are trademarks of their respective owners.

http://www.DigitalCoreDesign.com

http://www.dcd.pl

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