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DM9328N PDF预览

DM9328N

更新时间: 2024-11-05 22:40:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 移位寄存器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 51K
描述
Dual 8-Bit Shift Register

DM9328N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
风险等级:5.8Is Samacsys:N
其他特性:SHARED RESET BETWEEN 2 SHIFT REGISTERS计数方向:RIGHT
系列:93JESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.305 mm
逻辑集成电路类型:SERIAL IN SERIAL OUT最大频率@ Nom-Sup:20000000 Hz
位数:8功能数量:2
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):35 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mm最小 fmax:20 MHz
Base Number Matches:1

DM9328N 数据手册

 浏览型号DM9328N的Datasheet PDF文件第2页浏览型号DM9328N的Datasheet PDF文件第3页浏览型号DM9328N的Datasheet PDF文件第4页浏览型号DM9328N的Datasheet PDF文件第5页 
October 1988  
Revised February 2000  
DM9328  
Dual 8-Bit Shift Register  
General Description  
The DM9328 is a high speed serial storage element provid-  
ing 16 bits of storage in the form of two 8-bit registers. The  
multifunctional capability of this device is provided by sev-  
eral features: 1) additional gating is provided at the input to  
both shift registers so that the input is easily multiplexed  
between two sources; 2) the clock of each register may be  
provided separately or together; 3) both the true and com-  
plementary outputs are provided from each 8-bit register,  
and both registers may be master cleared from a common  
input.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM9328N  
N16E  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Logic Symbol  
Connection Diagram  
V
= Pin 16  
CC  
GND = Pin 8  
Pin Descriptions  
Pin Names  
Description  
Data Select Input  
S
D0, D1  
CP  
Data Inputs  
Clock Pulse Input (Active HIGH)  
Common (Pin 9)  
Separate (Pins 7 and 10)  
Master Reset Input (Active LOW)  
Last Stage Output  
MR  
Q7  
Q7  
Complementary Output  
© 2000 Fairchild Semiconductor Corporation  
DS009793  
www.fairchildsemi.com  

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