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DM81LS96AWM PDF预览

DM81LS96AWM

更新时间： 2024-11-25 22:29:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 74K
描述
3-STATE Octal Buffer

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DM81LS96AWM 数据手册

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September 1991  
Revised May 1999  
DM81LS95A • DM81LS96A • DM81LS97A  
3-STATE Octal Buffer  
General Description  
Features  
■ Typical power dissipation  
DM81LS95A, DM81LS97A  
DM81LS96A  
These devices provide eight, two-input buffers in each  
package. All employ low-power-Schottky TTL technology.  
One of the two inputs to each buffer is used as a control  
line to gate the output into the high-impedance state, while  
the other input passes the data through the buffer. The  
DM81LS95A and DM81LS97A present true data at the out-  
puts, while the DM81LS96A is inverting. On the  
DM81LS95A and DM81LS96A versions, all eight 3-STATE  
enable lines are common, with access through a 2-input  
NOR gate. On the DM81LS97A version, four buffers are  
enabled from one common line, and the other four buffers  
are enabled form another common line. In all cases the  
outputs are placed in the 3-STATE condition by applying a  
high logic level to the enable pins.  
80 mW  
65 mW  
■ Typical propagation delay  
DM81LS95A, DM81LS97A  
DM81LS96A  
15 ns  
10 ns  
■ Low power-Schottky, 3-STATE technology  
Ordering Code:  
Order Number Package Number  
Package Description  
DM81LS95AWM  
DM81LS95AN  
DM81LS96AWM  
DM81LS96AN  
DM81LS97AN  
M20B  
N20A  
M20B  
N20A  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
DM81LS95A and DM92LS96A  
Pin Names Descriptions  
A1–A8  
Y1–Y8  
Inputs  
Outputs  
Active LOW Output Enables (Note 1)  
G1–G2  
Note 1: Both G1 and G2 must be LOW for outputs to be enabled.  
DM81LS97A  
Pin Names  
A1–A8  
Descriptions  
Inputs  
Y1–Y8  
Outputs  
Active LOW Output Enable (Y1–Y4)  
Active LOW Output Enable (Y5–Y8)  
G1  
G2  
© 1999 Fairchild Semiconductor Corporation  
DS006435  
www.fairchildsemi.com  
1234567

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DM81LS96AWM 替代型号

型号 品牌 替代类型 描述 数据表
DM81LS96AWMX FAIRCHILD

功能相似

 8-Bit Inverting Buffer/Driver

与DM81LS96AWM相关器件

型号 品牌 获取价格 描述 数据表
DM81LS96AWMX FAIRCHILD

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 		8-Bit Inverting Buffer/Driver
DM81LS96J AMD

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 		Three-State Octal Buffers
DM81LS96J TI

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 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,CERAMIC
DM81LS96J/A+ TI

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 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,CERAMIC
DM81LS96N AMD

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 		Three-State Octal Buffers
DM81LS96N NSC

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 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,PLASTIC
DM81LS96N/A+ NSC

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 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,PLASTIC
DM81LS96N/A+ TI

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 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,PLASTIC
DM81LS96N/B+ NSC

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 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,PLASTIC
DM81LS96N/B+ TI

获取价格

 		IC,BUFFER/DRIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,PLASTIC

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