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DM74S10

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DM74S10 数据手册

August 1986

Revised April 2000

DM74S10

Triple 3-Input NAND Gate

General Description

This device contains three independent gates each of

which performs the logic NAND function.

Ordering Code:

Order Number Package Number

Package Description

DM74S10

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

Function Table

Y = ABC

Inputs

Output

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

DS006446

www.fairchildsemi.com

12 3

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型号	品牌	获取价格	描述	数据表
DM74S109N	TI	获取价格	S SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16, PLA
DM74S10J	ETC	获取价格	Triple 3-input NAND Gate
DM74S10J/A+	ETC	获取价格	Triple 3-input NAND Gate
DM74S10N	ETC	获取价格	Triple 3-input NAND Gate
DM74S10N/A+	ETC	获取价格	Triple 3-input NAND Gate
DM74S10N/B+	ETC	获取价格	Triple 3-input NAND Gate
DM74S11	FAIRCHILD	获取价格	Triple 3-Input AND Gate
DM74S112	FAIRCHILD	获取价格	Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complement
DM74S112J	ETC	获取价格	J-K-Type Flip-Flop
DM74S112J/A+	ETC	获取价格	J-K-Type Flip-Flop