DM74LS90N

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DM74LS90N 数据手册

June 1989

DM74LS90/DM74LS93

Decade and Binary Counters

General Description

Each of these monolithic counters contains four master-

slave flip-flops and additional gating to provide a divide-by-

two counter and a three-stage binary counter for which the

count cycle length is divide-by-five for the ’LS90 and divide-

by-eight for the ’LS93.

count pulses are applied to input A and the outputs are as

described in the appropriate truth table. A symmetrical di-

vide-by-ten count can be obtained from the ’LS90 counters

by connecting the Q output to the A input and applying the

input count to the B input which gives a divide-by-ten square

wave at output Q .

All of these counters have a gated zero reset and the LS90

also has gated set-to-nine inputs for use in BCD nine’s com-

plement applications.

Features

Typical power dissipation 45 mW

To use their maximum count length (decade or four bit bina-

ry), the B input is connected to the Q output. The input

Count frequency 42 MHz

Connection Diagrams (Dual-In-Line Packages)

TL/F/6381–1

Order Number DM74LS90M or DM74LS90N

See NS Package Number M14A or N14A

TL/F/6381–2

Order Number DM74LS93M or DM74LS93N

See NS Package Number M14A or N14A

1995 National Semiconductor Corporation

TL/F/6381

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6 7...10

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型号	品牌	获取价格	描述	数据表
DM74LS90N/A+	ETC	获取价格	Asynchronous Up Counter
DM74LS90N/B+	ETC	获取价格	Asynchronous Up Counter
DM74LS92J	NSC	获取价格	IC,COUNTER,UP,MODULO-12,LS-TTL,DIP,14PIN,CERAMIC
DM74LS92J/A+	ETC	获取价格	Asynchronous Up Counter
DM74LS92N	NSC	获取价格	IC,COUNTER,UP,MODULO-12,LS-TTL,DIP,14PIN,PLASTIC
DM74LS92N/A+	ETC	获取价格	Asynchronous Up Counter
DM74LS92N/B+	ETC	获取价格	Asynchronous Up Counter
DM74LS93	NSC	获取价格	Decade and Binary Counters
DM74LS93J	TI	获取价格	IC,COUNTER,UP,4-BIT BINARY,LS-TTL,DIP,14PIN,CERAMIC
DM74LS93J/A+	ETC	获取价格	Asynchronous Up Counter