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DM74LS90MX PDF预览

DM74LS90MX

更新时间: 2024-11-04 23:47:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 64K
描述
Asynchronous Up Counter

DM74LS90MX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.29
其他特性:DIVIDE BY 2 AND DIVIDE BY 5 FUNCTIONS计数方向:UP
系列:LSJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:8.6235 mm
负载/预设输入:YES逻辑集成电路类型:DECADE COUNTER
最大频率@ Nom-Sup:10000000 Hz最大I(ol):0.008 A
工作模式:ASYNCHRONOUS位数:3
功能数量:2端子数量:14
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):15 mA传播延迟(tpd):60 ns
认证状态:Not Qualified座面最大高度:1.753 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:NEGATIVE EDGE宽度:3.9 mm
最小 fmax:32 MHzBase Number Matches:1

DM74LS90MX 数据手册

 浏览型号DM74LS90MX的Datasheet PDF文件第2页浏览型号DM74LS90MX的Datasheet PDF文件第3页浏览型号DM74LS90MX的Datasheet PDF文件第4页浏览型号DM74LS90MX的Datasheet PDF文件第5页浏览型号DM74LS90MX的Datasheet PDF文件第6页 
August 1986  
Revised March 2000  
DM74LS90  
Decade and Binary Counters  
General Description  
Features  
Each of these monolithic counters contains four master-  
slave flip-flops and additional gating to provide a divide-by-  
two counter and a three-stage binary counter for which the  
count cycle length is divide-by-five for the DM74LS90.  
Typical power dissipation 45 mW  
Count frequency 42 MHz  
All of these counters have a gated zero reset and the  
DM74LS90 also has gated set-to-nine inputs for use in  
BCD nine’s complement applications.  
To use their maximum count length (decade or four bit  
binary), the B input is connected to the QA output. The  
input count pulses are applied to input A and the outputs  
are as described in the appropriate truth table. A symmetri-  
cal divide-by-ten count can be obtained from the  
DM74LS90 counters by connecting the QD output to the A  
input and applying the input count to the B input which  
gives a divide-by-ten square wave at output QA.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS90M  
DM74LS90N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Reset/Count Truth Table  
Reset Inputs  
Output  
R0(1)  
R0(2)  
R9(1)  
R9(2) QD QC QB QA  
H
H
X
X
L
H
H
X
L
L
X
H
X
L
X
L
L
L
L
L
L
L
L
L
L
L
H
L
H
H
COUNT  
COUNT  
COUNT  
COUNT  
X
X
L
X
L
L
X
L
X
X
© 2000 Fairchild Semiconductor Corporation  
DS006381  
www.fairchildsemi.com  

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