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DM74LS645WM PDF预览

DM74LS645WM

更新时间: 2024-09-29 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 55K
描述
Octal Bus Transceiver

DM74LS645WM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
风险等级:5.24Is Samacsys:N
其他特性:WITH DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:15 ns传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:7.5 mm
Base Number Matches:1

DM74LS645WM 数据手册

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August 1986  
Revised March 2000  
DM74LS645  
Octal Bus Transceiver  
General Description  
Features  
These octal bus transceivers are designed for asynchro-  
nous two-way communication between data buses. The  
devices transmit data from the A bus to the B bus or from  
the B bus to the A bus depending upon the level at the  
direction control (DIR) input. The enable input (G) can be  
used to disable the device so that the buses are effectively  
isolated.  
Bi-directional bus transceivers in high-density 20-pin  
packages  
Hysteresis at bus inputs improves noise margins  
3-STATE outputs  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS645WM  
DM74LS645N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Control  
Inputs  
DM74LS645  
G
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
H = HIGH Level  
L = LOW Level  
X = Irrelevant  
© 2000 Fairchild Semiconductor Corporation  
DS009056  
www.fairchildsemi.com  

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