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DM74LS645 PDF预览

DM74LS645

更新时间: 2024-11-27 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
5页 55K
描述
Octal Bus Transceiver

DM74LS645 数据手册

 浏览型号DM74LS645的Datasheet PDF文件第2页浏览型号DM74LS645的Datasheet PDF文件第3页浏览型号DM74LS645的Datasheet PDF文件第4页浏览型号DM74LS645的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74LS645  
Octal Bus Transceiver  
General Description  
Features  
These octal bus transceivers are designed for asynchro-  
nous two-way communication between data buses. The  
devices transmit data from the A bus to the B bus or from  
the B bus to the A bus depending upon the level at the  
direction control (DIR) input. The enable input (G) can be  
used to disable the device so that the buses are effectively  
isolated.  
Bi-directional bus transceivers in high-density 20-pin  
packages  
Hysteresis at bus inputs improves noise margins  
3-STATE outputs  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS645WM  
DM74LS645N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Control  
Inputs  
DM74LS645  
G
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
H = HIGH Level  
L = LOW Level  
X = Irrelevant  
© 2000 Fairchild Semiconductor Corporation  
DS009056  
www.fairchildsemi.com  

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3-STATE 4-by-4 Register File