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DM74LS573WMX PDF预览

DM74LS573WMX

更新时间: 2024-11-27 23:47:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 52K
描述
8-Bit D-Type Latch

DM74LS573WMX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
风险等级:5.64Is Samacsys:N
系列:LSJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):50 mAProp。Delay @ Nom-Sup:27 ns
传播延迟(tpd):25 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

DM74LS573WMX 数据手册

 浏览型号DM74LS573WMX的Datasheet PDF文件第2页浏览型号DM74LS573WMX的Datasheet PDF文件第3页浏览型号DM74LS573WMX的Datasheet PDF文件第4页浏览型号DM74LS573WMX的Datasheet PDF文件第5页 
October 1988  
Revised March 2000  
DM74LS573  
Octal D-Type Latch with 3-STATE Outputs  
General Description  
The DM74LS573 is a high speed octal latch with buffered  
common Latch Enable (LE) and buffered common Output  
Enable (OE) inputs.  
Features  
Inputs and outputs on opposite sides of package allow-  
ing easy interface with microprocessors  
Useful as input or output port for microprocessors  
Functionally identical to DM74LS373  
This device is functionally identical to the DM74LS373, but  
has different pinouts.  
Input clamp diodes limit high speed termination effects  
Fully TTL and CMOS compatible  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS573WM  
DM74LS573N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
V
= Pin 20  
CC  
GND = Pin 10  
Pin Descriptions  
Function Tables  
Pin Names  
Description  
Output  
Latch  
Output  
D
D0–D7  
LE  
Data Inputs  
Enable  
Enable  
O
H
Latch Enable Input (Active HIGH)  
3-STATE Output Enable Input (Active LOW)  
3-STATE Latch Outputs  
L
L
H
H
L
H
L
OE  
L
O0–O7  
L
X
X
QO  
Z
H
X
L = LOW State  
H = HIGH State  
X = Don't Care  
Z = High Impedance State  
= Previous Condition of O  
Q
O
© 2000 Fairchild Semiconductor Corporation  
DS009814  
www.fairchildsemi.com  

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