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DM74LS533N PDF预览

DM74LS533N

更新时间: 2024-11-01 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 52K
描述
Octal Transparent Latch with 3-STATE Outputs

DM74LS533N 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.63
Is Samacsys:N系列:LS
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
长度:26.075 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):46 mAProp。Delay @ Nom-Sup:23 ns
传播延迟(tpd):25 ns认证状态:Not Qualified
座面最大高度:5.08 mm子类别:FF/Latches
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

DM74LS533N 数据手册

 浏览型号DM74LS533N的Datasheet PDF文件第2页浏览型号DM74LS533N的Datasheet PDF文件第3页浏览型号DM74LS533N的Datasheet PDF文件第4页 
October 1988  
Revised March 2000  
DM74LS533  
Octal Transparent Latch with 3-STATE Outputs  
General Description  
Features  
The DM74LS533 consists of eight latches with 3-STATE  
outputs for bus organized system applications. The flip-  
flops appear transparent to the data when Latch Enable  
(LE) is HIGH. When LE is LOW, the data that meets the  
setup times is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH the bus  
output is in the high impedance state. The DM74LS533 is  
the same as the DM74LS373, except that the outputs are  
inverted. For detailed specifications please see the  
DM74LS373 data sheet, but note that the propagation  
delays from data to output are 5.0 ns longer for the  
DM74LS533 than for the DM74LS373.  
Eight latches in a single package  
3-STATE outputs for bus interfacing  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS533WM  
DM74LS533N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Connection Diagram  
V
= Pin 20  
CC  
GND = Pin 10  
Pin Descriptions  
Function Table  
Pin Names  
Description  
OUTPUT  
Latch  
D
Output  
D0, D7  
LE  
Data Inputs  
Enable  
Enable  
O
L
Latch Enable Input (Active HIGH)  
Output Enable Input (Active LOW)  
Complementary 3-STATE Outputs  
L
L
H
H
L
H
L
OE  
H
O0–O7  
L
X
X
QO  
Z
H
X
L = LOW State  
H = HIGH State  
X = Don't Care  
Z = High Impedance State  
Q
= Previous Condition of O  
O
© 2000 Fairchild Semiconductor Corporation  
DS009811  
www.fairchildsemi.com  

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