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DM74LS461

更新时间: 2024-11-27 23:00:43
品牌 Logo 应用领域
美国国家半导体 - NSC 计数器
页数 文件大小 规格书
4页 123K
描述
Octal Counter

DM74LS461 数据手册

 浏览型号DM74LS461的Datasheet PDF文件第2页浏览型号DM74LS461的Datasheet PDF文件第3页浏览型号DM74LS461的Datasheet PDF文件第4页 
July 1989  
DM54LS461/DM74LS461 Octal Counter  
General Description  
The LS461 is an 8-bit synchronous counter with parallel  
Two or more LS461 octal counters may be cascaded to  
provide larger counters. The operation codes were chosen  
load, clear, and hold capability. Two function select inputs  
(I , I ) provide one of four operations which occur synchro-  
such that when I is HIGH, I may be used to select be-  
1 0  
tween LOAD and INCREMENT as in a program counter  
(JUMP/INCREMENT).  
0
1
nously on the rising edge of the clock (CK).  
The LOAD operation loads the inputs (D D ) into the out-  
7
0
put register (Q Q ). The CLEAR operation resets the out-  
7
0
Features/Benefits  
Y
put register to all LOWs. The HOLD operation holds the  
previous value regardless of clock transitions. The INCRE-  
MENT operation adds one to the output register when the  
Octal counter for microprogram-counter, DMA controller  
and general purpose counting applications  
e
carry-in input is TRUE (CI  
is a HOLD. The carry-out (CO) is TRUE (CO  
the output register (Q Q ) is all HIGHs, otherwise FALSE  
LOW), otherwise the operation  
Y
8 bits match byte boundaries  
e
LOW) when  
Y
Bus-structured pinout  
7
0
Y
24-pin Skinny Dip saves space  
e
(CO  
HIGH).  
Y
TRI-STATE outputs drive bus lines  
É
Low current PNP inputs reduce loading  
The output register (Q Q ) is enabled when OE is LOW,  
0
7
Y
and disabled (HI-Z) when OE is HIGH. The output drivers  
will sink the 24 mA required for many bus interface stand-  
ards.  
Y
Expandable in 8-bit increments  
Connection Diagram  
Standard Test Load  
Top View  
TL/L/8334–2  
TL/L/8334–1  
Order Number DM54LS461J,  
DM74LS461J or DM74LS461N  
See NS Package Number J24F or N24C  
Function Table  
OE CK I1 I0 CI D7D0 Q7Q0  
Operation  
H
L
L
L
L
L
X
X
L
X
L
X
X
X
X
H
L
X
X
X
D
X
X
Z
L
HI-Z  
CLEAR  
HOLD  
LOAD  
HOLD  
u
u
u
u
u
L
H
L
Q
D
Q
H
H
H
H
H
Q plus 1 INCREMENT  
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.  
C
1995 National Semiconductor Corporation  
TL/L/8334  
RRD-B30M115/Printed in U. S. A.  

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