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DM74LS373SJ PDF预览

DM74LS373SJ

更新时间： 2024-11-30 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器
页数 文件大小 规格书
8页 91K
描述
3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops

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中文翻译

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DM74LS373SJ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP20,.3
针数：20Reach Compliance Code：unknown
风险等级：5.26系列：LS
JESD-30 代码：R-PDSO-G20JESD-609代码：e0
长度：12.6 mm负载电容（CL）：45 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V最大电源电流（ICC）：40 mA
Prop。Delay @ Nom-Sup：18 ns传播延迟（tpd）：27 ns
认证状态：Not Qualified座面最大高度：2.1 mm
子类别：FF/Latches最大供电电压 (Vsup)：5.25 V
最小供电电压 (Vsup)：4.75 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

DM74LS373SJ 数据手册

 浏览型号DM74LS373SJ的Datasheet PDF文件第2页浏览型号DM74LS373SJ的Datasheet PDF文件第3页浏览型号DM74LS373SJ的Datasheet PDF文件第4页浏览型号DM74LS373SJ的Datasheet PDF文件第5页浏览型号DM74LS373SJ的Datasheet PDF文件第6页浏览型号DM74LS373SJ的Datasheet PDF文件第7页 
April 1986  
Revised March 2000  
DM74LS373 • DM74LS374  
3-STATE Octal D-Type Transparent Latches  
and Edge-Triggered Flip-Flops  
General Description  
Features  
■ Choice of 8 latches or 8 D-type flip-flops in a single  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
package  
■ 3-STATE bus-driving outputs  
■ Full parallel-access for loading  
■ Buffered control inputs  
■ P-N-P inputs reduce D-C loading on data lines  
The eight latches of the DM74LS373 are transparent D-  
type latches meaning that while the enable (G) is HIGH the  
Q outputs will follow the data (D) inputs. When the enable  
is taken LOW the output will be latched at the level of the  
data that was set up.  
The eight flip-flops of the DM74LS374 are edge-triggered  
D-type flip flops. On the positive transition of the clock, the  
Q outputs will be set to the logic states that were set up at  
the D inputs.  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high-impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the latches or flip-flops. That is, the old data can be  
retained or new data can be entered even while the outputs  
are OFF.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS373WM  
DM74LS373SJ  
DM74LS373N  
DM74LS374WM  
DM74LS374SJ  
IDM29901NC  
M20B  
M20D  
N20A  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006431  
www.fairchildsemi.com  
12345678

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 		TRI-STATEE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
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DM74LS374J NSC

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 		IC,FLIP-FLOP,OCTAL,D TYPE,LS-TTL,DIP,20PIN,CERAMIC
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