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DM74LS126AMX PDF预览

DM74LS126AMX

更新时间: 2024-09-20 23:47:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 51K
描述
4-Bit Buffer/Driver

DM74LS126AMX 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.28
控制类型:ENABLE HIGH系列:LS
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):22 mA
Prop。Delay @ Nom-Sup:18 ns传播延迟(tpd):22 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

DM74LS126AMX 数据手册

 浏览型号DM74LS126AMX的Datasheet PDF文件第2页浏览型号DM74LS126AMX的Datasheet PDF文件第3页浏览型号DM74LS126AMX的Datasheet PDF文件第4页 
August 1986  
Revised March 2000  
DM74LS126A  
Quad 3-STATE Buffer  
General Description  
This device contains four independent gates each of which  
performs a non-inverting buffer function. The outputs have  
the 3-STATE feature. When enabled, the outputs exhibit  
the low impedance characteristics of a standard LS output  
with additional drive capability to permit the driving of bus  
lines without external resistors. When disabled, both the  
output transistors are turned OFF presenting a high-imped-  
ance state to the bus line. Thus the output will act neither  
as a significant load nor as a driver. To minimize the possi-  
bility that two outputs will attempt to take a common bus to  
opposite logic levels, the disable time is shorter than the  
enable time of the outputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS126AM  
DM74LS126AN  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = A  
Inputs  
Output  
A
L
C
H
H
L
Y
L
H
X
H
Hi-Z  
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either LOW or HIGH Logic Level  
Hi-Z = 3-STATE (Outputs are disabled)  
© 2000 Fairchild Semiconductor Corporation  
DS006388  
www.fairchildsemi.com  

DM74LS126AMX 替代型号

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