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DM74LS126ACW PDF预览

DM74LS126ACW

更新时间: 2024-09-21 12:58:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
4页 51K
描述
Bus Driver, LS Series, 4-Func, 1-Bit, True Output, TTL, WAFER

DM74LS126ACW 技术参数

生命周期:Obsolete零件包装代码:WAFER
包装说明:DIE,Reach Compliance Code:unknown
风险等级:5.73Is Samacsys:N
系列:LSJESD-30 代码:X-XUUC-N14
逻辑集成电路类型:BUS DRIVER位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:UNSPECIFIED
封装代码:DIE封装形状:UNSPECIFIED
封装形式:UNCASED CHIP传播延迟(tpd):22 ns
认证状态:Not Qualified最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子形式:NO LEAD
端子位置:UPPERBase Number Matches:1

DM74LS126ACW 数据手册

 浏览型号DM74LS126ACW的Datasheet PDF文件第2页浏览型号DM74LS126ACW的Datasheet PDF文件第3页浏览型号DM74LS126ACW的Datasheet PDF文件第4页 
August 1986  
Revised March 2000  
DM74LS126A  
Quad 3-STATE Buffer  
General Description  
This device contains four independent gates each of which  
performs a non-inverting buffer function. The outputs have  
the 3-STATE feature. When enabled, the outputs exhibit  
the low impedance characteristics of a standard LS output  
with additional drive capability to permit the driving of bus  
lines without external resistors. When disabled, both the  
output transistors are turned OFF presenting a high-imped-  
ance state to the bus line. Thus the output will act neither  
as a significant load nor as a driver. To minimize the possi-  
bility that two outputs will attempt to take a common bus to  
opposite logic levels, the disable time is shorter than the  
enable time of the outputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS126AM  
DM74LS126AN  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = A  
Inputs  
Output  
A
L
C
H
H
L
Y
L
H
X
H
Hi-Z  
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either LOW or HIGH Logic Level  
Hi-Z = 3-STATE (Outputs are disabled)  
© 2000 Fairchild Semiconductor Corporation  
DS006388  
www.fairchildsemi.com  

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