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DM74LS05SJ PDF预览

DM74LS05SJ

更新时间: 2024-11-03 23:00:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 65K
描述
Hex Inverters with Open-Collector Outputs

DM74LS05SJ 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:5.30 MM, EIAJ TYPE2, SOP-14
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.27
Is Samacsys:N系列:LS
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:10.2 mm逻辑集成电路类型:INVERTER
最大I(ol):0.008 A功能数量:6
输入次数:1端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:OPEN-COLLECTOR封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V最大电源电流(ICC):6.6 mA
Prop。Delay @ Nom-Sup:45 ns传播延迟(tpd):20 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.1 mm子类别:Gates
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:5.3 mmBase Number Matches:1

DM74LS05SJ 数据手册

 浏览型号DM74LS05SJ的Datasheet PDF文件第2页浏览型号DM74LS05SJ的Datasheet PDF文件第3页浏览型号DM74LS05SJ的Datasheet PDF文件第4页浏览型号DM74LS05SJ的Datasheet PDF文件第5页 
August 1986  
Revised March 2000  
DM74LS05  
Hex Inverters with Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
This device contains six independent gates each of which  
performs the logic INVERT function. The open-collector  
outputs require external pull-up resistors for proper logical  
operation.  
Where:  
N1 (IOH) = total maximum output high current  
for all outputs tied to pull-up resistor  
N2 (IIH) = total maximum input high current for  
all inputs tied to pull-up resistor  
N3 (IIL) = total maximum input low current for  
all inputs tied to pull-up resistor  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS05M  
DM74LS05SJ  
DM74LS05N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = A  
Input  
Output  
A
L
Y
H
L
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006346  
www.fairchildsemi.com  

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