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DM74AS652WMX

更新时间： 2024-11-15 12:53:27

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器逻辑集成电路光电二极管输出元件
页数	文件大小	规格书
8页	74K
描述
Octal Bus Transceiver and Register

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中文翻译

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数据手册
替代型号

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DM74AS652WMX 数据手册

October 1986

Revised July 2003

DM74AS651 • DM74AS652

Octal Bus Transceiver and Register

General Description

Features

These devices incorporate an octal transceiver and an

octal D-type register configured to enable transmission of

data from bus to bus or internal register to bus. The

DM74AS651 offers 64-Industrial grade product guarantee-

ing performance from −40°C to +85°C.

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

These bus transceivers feature totem-pole 3-STATE out-

puts designed specifically for driving highly-capacitive or

relatively low-impedance loads. The high-impedance state

and increased high-logic-level drive provide these devices

with the capability of being connected directly to and driv-

ing the bus lines in a bus-organized system without need

for interface or pull-up components. They are particularly

attractive for implementing buffer registers, I/O ports, bidi-

rectional bus drivers, and working registers.

■ 3-STATE buffer-type outputs drive bus lines directly

■ Guaranteed performance over industrial temperature

range (−40°C to +85°C) in 64-grade products

The registers in the DM74AS651 and DM74AS652 are

edge-triggered D-type flip-flops. On the positive transition

of the clock (CAB or CBA), the input data is stored.

The SAB and SBA control pins are provided to select

whether real-time data or stored data is transferred. A LOW

input level selects real-time data and a HIGH level selects

stored data. The select controls have a “make before

break” configuration to eliminate a glitch which would nor-

mally occur in a typical multiplexer during the transition

between stored and real-time data.

The Enable (GAB and GBA) control pins provide four

modes of operation; real-time data transfer from bus A-to-

B, real-time data transfer from bus B-to-A, real-time bus A

and/or B data transfer to internal storage, or internal stored

data transfer to bus A and/or B.

Ordering Code:

Order Number Package Number

Package Description

DM74AS651WM

DM74AS651NT

DM74AS652WM

DM74AS652NT

M24B

N24C

M24B

N24C

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

DS006325

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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DM74AS652WMX 替代型号

型号	品牌	替代类型	描述	数据表
DM74AS652WM	FAIRCHILD	完全替代	Octal Bus Transceiver and Register
SN74AS652DWR	TI	功能相似	OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS
DM74AS651NT	FAIRCHILD	功能相似	Octal Bus Transceiver and Register

与DM74AS652WMX相关器件

型号	品牌	获取价格	描述	数据表
DM74AS74	FAIRCHILD	获取价格	Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74AS74J/A+	ETC	获取价格	Dual D-Type Flip-Flop
DM74AS74M	FAIRCHILD	获取价格	Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74AS74M/A+	ETC	获取价格	Dual D-Type Flip-Flop
DM74AS74M/B+	ETC	获取价格	Dual D-Type Flip-Flop
DM74AS74MX	ETC	获取价格	Dual D-Type Flip-Flop
DM74AS74N	FAIRCHILD	获取价格	Dual D-Type Positive-Edge-Triggered Flip-Flop with Preset and Clear
DM74AS74N/A+	ETC	获取价格	Dual D-Type Flip-Flop
DM74AS74N/B+	ETC	获取价格	Dual D-Type Flip-Flop
DM74AS74N_NL	FAIRCHILD	获取价格	D Flip-Flop, AS Series, 2-Func, Positive Edge Triggered, 1-Bit, Complementary Output, TTL,

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