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DM74AS374N PDF预览

DM74AS374N

更新时间: 2024-11-13 22:39:15
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管驱动
页数 文件大小 规格书
6页 63K
描述
Octal D-Type Edge-Triggered Flip-Flops

DM74AS374N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.32
系列:ASJESD-30 代码:R-PDIP-T20
JESD-609代码:e3长度:26.075 mm
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:125000000 Hz
最大I(ol):0.048 A位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE电源:5 V
最大电源电流(ICC):128 mA传播延迟(tpd):9 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
触发器类型:POSITIVE EDGE宽度:7.62 mm
Base Number Matches:1

DM74AS374N 数据手册

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October 1986  
Revised March 2000  
DM74AS374  
Octal D-Type Edge-Triggered Flip-Flops  
with 3-STATE Outputs  
General Description  
Features  
Switching specifications at 50 pF  
These 8-bit registers feature totem-pole 3-STATE outputs  
designed specifically for driving highly-capacitive or rela-  
tively low-impedance loads. The high-impedance state and  
increased high-logic-level drive provide these registers with  
the capability of being connected directly to and driving the  
bus lines in a bus-organized system without need for inter-  
face or pull-up components. They are particularly attractive  
for implementing buffer registers, I/O ports, bidirectional  
bus drivers, and working registers.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin-for-pin compatible with LS and ALS  
TTL counterparts  
Improved AC performance over LS and ALS TTL coun-  
terparts  
The eight flip-flops of the AS374 are edge-triggered D-type  
flip-flops. On the positive transition of the clock, the Q out-  
puts will be set to the logic states that were set up at the D  
inputs.  
3-STATE buffer-type outputs drive bus lines directly  
A buffered output control input can be used to place the  
eight outputs in either a normal logic state (HIGH or LOW  
logic levels) or a high impedance state. In the high-imped-  
ance state the outputs neither load nor drive the bus lines  
significantly.  
The output control does not affect the internal operation of  
the flip-flops. That is, the old data can be retained or new  
data can be entered even while the outputs are off.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS374WM  
DM74AS374N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
© 2000 Fairchild Semiconductor Corporation  
DS006310  
www.fairchildsemi.com  

DM74AS374N 替代型号

型号 品牌 替代类型 描述 数据表
DM74AS374WM FAIRCHILD

完全替代

Octal D-Type Edge-Triggered Flip-Flops
DM74AS373N FAIRCHILD

完全替代

Octal D-Type Transparent Latch with 3-STATE Outputs
SN74AS374DWR TI

类似代替

OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

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