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DM74AS1805WM PDF预览

DM74AS1805WM

更新时间: 2024-11-14 22:34:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 50K
描述
Hex 2-Input NOR Driver

DM74AS1805WM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.69
Is Samacsys:N系列:AS
JESD-30 代码:R-PDSO-G20JESD-609代码:e0
长度:12.8 mm逻辑集成电路类型:NOR GATE
最大I(ol):0.048 A功能数量:6
输入次数:2端子数量:20
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):32 mA
Prop。Delay @ Nom-Sup:4.3 ns传播延迟(tpd):4.3 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.65 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

DM74AS1805WM 数据手册

 浏览型号DM74AS1805WM的Datasheet PDF文件第2页浏览型号DM74AS1805WM的Datasheet PDF文件第3页浏览型号DM74AS1805WM的Datasheet PDF文件第4页 
July 1985  
Revised March 2000  
DM74AS1805  
Hex 2-Input NOR Driver  
General Description  
Features  
These devices contain six independent 2-Input drivers  
each of which performs the logic NOR function. The  
DM74AS1805 is equivalent to the DM74AS805B but the  
supply voltage and ground pins are centered in the pack-  
age. This positioning of the supply voltage and ground pins  
reduce the lead inductance of these pins. This reduction of  
lead inductance will minimize noise generated onto either  
the supply voltage or ground bus which is significant in high  
current switching applications.  
Switching specifications at 50 pF  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Centered VCC and GND configuration provides minimum  
lead inductance for high current switching applications  
High capacitive drive capability  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS1805WM  
DM74AS1805N  
M20B  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = A + B  
INPUTS  
OUTPUT  
A
L
B
L
Y
H
L
L
H
L
H
H
L
H
L
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS008618  
www.fairchildsemi.com  

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