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DM74AS163N PDF预览

DM74AS163N

更新时间: 2024-11-26 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 76K
描述
Synchronous 4-Bit Counter with Asynchronous Clear . Synchronous 4-Bit Counter

DM74AS163N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, MS-001, PLASTIC, DIP-16
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.49
Is Samacsys:N计数方向:UP
系列:ASJESD-30 代码:R-PDIP-T16
长度:19.304 mm负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:75000000 Hz
最大I(ol):0.02 A工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP16,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):53 mA传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Counters最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:75 MHz
Base Number Matches:1

DM74AS163N 数据手册

 浏览型号DM74AS163N的Datasheet PDF文件第2页浏览型号DM74AS163N的Datasheet PDF文件第3页浏览型号DM74AS163N的Datasheet PDF文件第4页浏览型号DM74AS163N的Datasheet PDF文件第5页浏览型号DM74AS163N的Datasheet PDF文件第6页浏览型号DM74AS163N的Datasheet PDF文件第7页 
April 1984  
Revised March 2000  
DM74AS161 • DM74AS163  
Synchronous 4-Bit Counter with Asynchronous Clear •  
Synchronous 4-Bit Counter  
The carry look ahead circuitry provides for cascading  
counters for n bit synchronous application without addi-  
General Description  
These synchronous presettable counters feature an inter-  
tional gating. Instrumental in accomplishing this function  
nal carry look ahead for application in high speed counting  
are two count-enable inputs (P and T) and a ripple carry  
designs. The DM74AS161 and DM74AS163 are 4-bit  
output. Both count-enable inputs must be HIGH to count.  
binary counters. The DM74AS161 clear asynchronously,  
The T input is fed forward to enable the ripple carry output.  
while the DM74AS163 clear synchronously. The carry out-  
The ripple carry output thus enabled will produce a high  
put is decoded to prevent spikes during normal counting  
level output pulse with a duration approximately equal to  
mode of operation. Synchronous operation is provided by  
the high level portion of QA output. This high level overflow  
having all flip-flops clocked simultaneously so that outputs  
ripple carry pulse can be used to enable successive cas-  
change coincident with each other when so instructed by  
caded stages. HIGH-to-LOW level transitions at the enable  
count enable inputs and internal gating. This mode of oper-  
P or T inputs of the DM74AS161 and DM74AS163, may  
ation eliminates the output counting spikes which are nor-  
occur regardless of the logic level on the clock.  
mally associated with asynchronous (ripple clock)  
The DM74AS161 and DM74AS163 feature a fully indepen-  
counters. A buffered clock input triggers the four flip-flops  
dent clock circuit. Changes made to control inputs (enable  
on the rising (positive-going) edge of the clock input wave-  
P or T, or load) that will modify the operating mode will  
form.  
have no effect until clocking occurs. The function of the  
These counters are fully programmable, that is, the outputs  
counter (whether enabled, disabled, loading or counting)  
may each be preset to either level. As presetting is syn-  
will be dictated solely by the conditions meeting the stable  
chronous, setting up a low level at the LOAD input disables  
set-up and hold times.  
the counter and causes the outputs to agree with set up  
data after the next clock pulse regardless of the levels of  
enable input. LOW-to-HIGH transitions at the LOAD input  
Features  
Switching specifications at 50 pF  
are perfectly acceptable regardless of the logic levels on  
the clock or enable inputs.  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
The DM74AS161 clear function is asynchronous. A low  
level at the clear input sets all four of the flip-flop outputs  
LOW regardless of the levels of clock, load or enable  
inputs. This counter is provided with a clear on power-up  
feature. The DM74AS163 clear function is synchronous;  
and a low level at the clear input sets all four of the flip-flop  
outputs LOW after the next clock pulse, regardless of the  
levels of enable inputs. This synchronous clear allows the  
count length to be modified easily, as decoding the maxi-  
mum count desired can be accomplished with one external  
NAND gate. The gate output is connected to the clear input  
to synchronously clear the counter to all LOW outputs.  
LOW-to-HIGH transitions at the clear input of the  
DM74AS163 is also permissible regardless of the levels of  
logic on the clock, enable or load inputs.  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin-for-pin compatible with Schottky  
and low power Schottky TTL counterpart  
Improved AC performance over Schottky and low power  
Schottky counterparts  
Synchronously programmable  
Internal look ahead for fast counting  
Carry output for n-bit cascading  
Synchronous counting  
Load control line  
ESD inputs  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74AS161M  
DM74AS161N  
DM74AS163M  
DM74AS163N  
M16A  
N16E  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006291  
www.fairchildsemi.com  

DM74AS163N 替代型号

型号 品牌 替代类型 描述 数据表
DM74AS163MX FAIRCHILD

完全替代

Synchronous Up Counter
DM74AS163M FAIRCHILD

完全替代

Synchronous 4-Bit Counter with Asynchronous Clear . Synchronous 4-Bit Counter
DM74AS161N FAIRCHILD

完全替代

Synchronous 4-Bit Counter with Asynchronous Clear . Synchronous 4-Bit Counter

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