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DM74ALS645AN_NL PDF预览

DM74ALS645AN_NL

更新时间: 2024-09-15 12:58:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
4页 51K
描述
Bus Transceiver, ALS Series, 1-Func, 8-Bit, True Output, TTL, PDIP20, 0.300 INCH, PLASTIC, MS-001, DIP-20

DM74ALS645AN_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP20,.3
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.26
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:ALSJESD-30 代码:R-PDIP-T20
JESD-609代码:e3长度:26.075 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.024 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:5 V最大电源电流(ICC):58 mA
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
翻译:N/A宽度:7.62 mm
Base Number Matches:1

DM74ALS645AN_NL 数据手册

 浏览型号DM74ALS645AN_NL的Datasheet PDF文件第2页浏览型号DM74ALS645AN_NL的Datasheet PDF文件第3页浏览型号DM74ALS645AN_NL的Datasheet PDF文件第4页 
March 1987  
Revised February 2000  
DM74ALS645A  
Octal Bus Transceivers  
General Description  
Features  
These octal bus transceivers are designed for asynchro-  
nous two-way communication between data busses. These  
devices transmit data from the A bus to the B bus or from  
the B bus to the A bus depending upon the level at the  
direction control (DIR) input. The enable input (G) can be  
used to disable the device so the busses are effectively  
isolated.  
Advanced Oxide-isolated Ion-implanted Schottky TTL  
process  
Switching performance is guaranteed over full tempera-  
ture and VCC supply range  
Switching performance specified at 50 pF  
PNP input design reduces input loading  
Ordering Code:  
Order Number  
DM74ALS645AWM  
DM74ALS645AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Function Table  
Control  
Inputs  
Operation  
G
L
DIR  
L
B Data to A Bus  
A Data to B Bus  
Isolation  
L
H
H
X
L = LOW Logic Level  
H = HIGH Logic Level  
X = Either LOW or HIGH Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS009304  
www.fairchildsemi.com  

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