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DM74ALS640AWM PDF预览

DM74ALS640AWM

更新时间: 2024-10-29 22:07:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 51K
描述
Inverting Octal Bus Transceiver

DM74ALS640AWM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:0.300 INCH, MS-013, SOIC-20
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:ALS
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):55 mA
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):11 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

DM74ALS640AWM 数据手册

 浏览型号DM74ALS640AWM的Datasheet PDF文件第2页浏览型号DM74ALS640AWM的Datasheet PDF文件第3页浏览型号DM74ALS640AWM的Datasheet PDF文件第4页 
August 1985  
Revised February 2000  
DM74ALS640A  
Inverting Octal Bus Transceiver  
General Description  
Features  
This inverting octal bus transceiver is designed for asyn-  
chronous two-way communication between data busses.  
This device transmits data from the A bus to the B bus or  
from the B bus to the A bus depending upon the level at the  
direction control (DIR) input. The enable input (G) can be  
used to disable the device so the busses are effectively  
isolated.  
Advanced Oxide-isolated Ion-implanted Schottky TTL  
process  
Switching performance is guaranteed over full tempera-  
ture and VCC supply range  
Switching performance specified at 50 pF  
PNP input design reduces input loading  
Ordering Code:  
Order Number  
DM74ALS640AWM  
DM74ALS640AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Function Table  
Control  
Inputs  
Operation  
G
DIR  
L
L
B Data to A Bus  
L
H
X
A Data to B Bus  
Isolation  
H
L = LOW Logic Level  
H = HIGH Logic Level  
X = Either LOW or HIGH Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS008640  
www.fairchildsemi.com  

DM74ALS640AWM 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS640BNSRG4 TI

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SN74ALS640B-1NSR TI

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OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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