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DM74ALS640 PDF预览

DM74ALS640

更新时间: 2024-10-29 22:56:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线收发器
页数 文件大小 规格书
4页 51K
描述
Inverting Octal Bus Transceiver

DM74ALS640 数据手册

 浏览型号DM74ALS640的Datasheet PDF文件第2页浏览型号DM74ALS640的Datasheet PDF文件第3页浏览型号DM74ALS640的Datasheet PDF文件第4页 
August 1985  
Revised February 2000  
DM74ALS640A  
Inverting Octal Bus Transceiver  
General Description  
Features  
This inverting octal bus transceiver is designed for asyn-  
chronous two-way communication between data busses.  
This device transmits data from the A bus to the B bus or  
from the B bus to the A bus depending upon the level at the  
direction control (DIR) input. The enable input (G) can be  
used to disable the device so the busses are effectively  
isolated.  
Advanced Oxide-isolated Ion-implanted Schottky TTL  
process  
Switching performance is guaranteed over full tempera-  
ture and VCC supply range  
Switching performance specified at 50 pF  
PNP input design reduces input loading  
Ordering Code:  
Order Number  
DM74ALS640AWM  
DM74ALS640AN  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
N20A  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Function Table  
Control  
Inputs  
Operation  
G
DIR  
L
L
B Data to A Bus  
L
H
X
A Data to B Bus  
Isolation  
H
L = LOW Logic Level  
H = HIGH Logic Level  
X = Either LOW or HIGH Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS008640  
www.fairchildsemi.com  

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