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DM74ALS540AWM

更新时间: 2024-11-03 22:07:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
5页 64K
描述
Octal Inverting Buffer and Line Driver with 3-STATE Outputs

DM74ALS540AWM 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.31
控制类型:ENABLE LOW系列:ALS
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.4
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):22 mAProp。Delay @ Nom-Sup:12 ns
传播延迟(tpd):12 ns认证状态:Not Qualified
座面最大高度:2.65 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.5 mm
Base Number Matches:1

DM74ALS540AWM 数据手册

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October 1986  
Revised February 2000  
DM74ALS540A  
Octal Inverting Buffer and Line Driver  
with 3-STATE Outputs  
General Description  
Features  
Advanced oxide-isolated, ion-implanted Schottky TTL  
This octal buffer and line driver is designed to have the per-  
formance of the DM74ALS240A series and, at the same  
time, offer a pinout with inputs and outputs on opposite  
sides of the package. This arrangement greatly enhances  
printed circuit board layout. The 3-STATE control gate is a  
2-input NOR such that if either G1 or G2 is HIGH, all eight  
outputs are in the high impedance state.  
process  
Switching performance is guaranteed over full tempera-  
ture and VCC supply range  
Data flow-thru pinout (All inputs on opposite side from  
outputs)  
P-N-P inputs reduce DC loading  
Ordering Code:  
Order Number  
Package Number Package Description  
DM74ALS540AWM  
DM74ALS540ASJ  
DM74ALS540AN  
M20B  
M20D  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Output  
G 1  
H
G 2  
X
A
X
X
L
Y
Hi-Z  
Hi-Z  
H
X
H
L
L
L
L
H
L
H = HIGH Logic Level  
L = LOW Logic Level  
X = Don't Care (Either HIGH or LOW Logic Level)  
Hi-Z = High Impedance (OFF) State  
© 2000 Fairchild Semiconductor Corporation  
DS009170  
www.fairchildsemi.com  

DM74ALS540AWM 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALS540NSR TI

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SN74ALS540DW TI

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