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DM74ALS169

更新时间: 2024-11-05 22:56:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 计数器
页数 文件大小 规格书
7页 72K
描述
Synchronous Four-Bit Up/Down Counters

DM74ALS169 数据手册

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April 1984  
Revised April 2000  
DM74ALS169B  
Synchronous Four-Bit Up/Down Counters  
General Description  
Features  
These synchronous presettable counters feature an inter-  
nal carry look ahead for cascading in high speed counting  
applications. The DM74ALS169B is a four-bit binary up/  
down counter. The carry output is decoded to prevent  
spikes during normal mode of counting operation. Synchro-  
nous operation is provided so that outputs change coinci-  
dent with each other when so instructed by count enable  
inputs and internal gating. This mode of operation elimi-  
nates the output counting spikes which are normally asso-  
Switching specifications at 50 pF  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin-for-pin compatible with Schottky  
and low power Schottky TTL counterpart  
Improved AC performance over Schottky and low power  
Schottky counterparts  
ciated with asynchronous (ripple clock) counters.  
A
buffered clock input triggers the four flip-flops on the rising  
(positive going) edge of clock input waveform.  
Synchronously programmable  
Internal look ahead for fast counting  
Carry output for n-bit cascading  
Synchronous counting  
These counters are fully programmable; that is, the outputs  
may each be preset either HIGH or LOW. The load input  
circuitry allows loading with carry-enable output of cas-  
caded counters. As loading is synchronous, setting up a  
low level at the load input disables the counter and causes  
the outputs to agree with the data inputs after the next  
clock pulse.  
ESD inputs  
The carry look-ahead circuitry permits cascading counters  
for n-bit synchronous applications without additional gating.  
Both count enable inputs (P and T) must be LOW to count.  
The direction of the count is determined by the level of the  
up/down input. When the input is HIGH, the counter counts  
UP; when LOW, it counts DOWN. Input T is fed forward to  
enable the carry outputs. The carry output thus enabled will  
produce a low level output pulse with a duration approxi-  
mately equal to the high portion of the QA output when  
counting UP, and approximately equal to the low portion of  
the QA when counting DOWN. This low level overflow carry  
pulse can be used to enable successively cascaded  
stages. Transitions at the enable P or T inputs are allowed  
regardless of the level of the clock input.  
The control functions for these counters are fully synchro-  
nous. Changes at control inputs (enable P, enable T, load,  
up/down) which modify the operating mode have no effect  
until clocking occurs. The function of the counter (whether  
enabled, disabled, loading or counting) will be dictated  
solely by the conditions meeting the stable setup and hold  
times.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS169BM  
DM74ALS169BN  
M16A  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2000 Fairchild Semiconductor Corporation  
DS006207  
www.fairchildsemi.com  

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