DM74ALS165M_NL

更新时间： 2024-09-15 13:07:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		移位寄存器
页数	文件大小	规格书
6页	67K
描述
Parallel In Serial Out, ALS Series, 8-Bit, Right Direction, Complementary Output, TTL, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16

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技术参数
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DM74ALS165M_NL 技术参数

生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP,	针数：	16
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.72	Is Samacsys：	N
其他特性：	CLOCK INHIBIT	计数方向：	RIGHT
系列：	ALS	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e3/e4	长度：	9.9 mm
逻辑集成电路类型：	PARALLEL IN SERIAL OUT	位数：	8
功能数量：	1	端子数量：	16
最高工作温度：	70 °C	最低工作温度：
输出特性：	3-STATE	输出极性：	COMPLEMENTARY
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
传播延迟（tpd）：	14 ns	认证状态：	Not Qualified
座面最大高度：	1.75 mm	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	TTL
温度等级：	COMMERCIAL	端子面层：	MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	触发器类型：	POSITIVE EDGE
宽度：	3.9 mm	最小 fmax：	45 MHz
Base Number Matches：	1

DM74ALS165M_NL 数据手册

January 1986

Revised February 2000

DM74ALS165

8-Bit Parallel In/Serial Out Shift Register

General Description

The DM74ALS165 is an 8-bit serial register that, when

Features

■ Complementary outputs

clocked, shifts the data toward serial output, Q_H. Parallel-in

■ Direct overriding load (data) inputs

■ Gated clock inputs

access to each stage is provided by eight individual direct

data inputs that are enabled by a low level at the SH/LD

input. The DM74ALS165 also features a clock inhibit func-

tion and a complemented serial output, Q_H.

■ Parallel-to-serial data conversion

Clocking is accomplished by a LOW-to-HIGH transition of

the CLK input while SH/LD is held HIGH and CLK INH is

held LOW. The functions of the CLK and CLK INH (clock

inhibit) inputs are interchangeable. Since a LOW CLK input

and a LOW-to-HIGH transition of CLK INH will also accom-

plish clocking, CLK INH should be changed to the high

level only while the CLK input is HIGH. Parallel loading is

inhibited when SH/LD is held HIGH. The parallel inputs to

the register are enabled while SH/LD is LOW indepen-

dently of the levels of CLK, CLK INH, or SER inputs.

Ordering Code:

Order Number Package Number

Package Description

DM74ALS165M

DM74ALS165N

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Internal

Shift/ Clock Clock Serial Parallel Outputs Output

A...H

Q_A

Q_B

Q_H

Load Inhibit

↑

a...h

Q_A0Q_B0

Q_H0

Q_Gn

Q_H0

Q_An

↑

Q_A0Q_B0

H = HIGH Level (steady-state),

L = LOW Level (steady-state)

X = Don't Care (any input, including transitions)

↑ = Transition from LOW-to-HIGH level

a...h = The level of steady-state input at inputs A through H, respectively

, Q , Q = The level of Q , Q , or Q , respectively, before the

B0 H0 A B H

indicated steady-state input conditions were established

, Q = The level of Q or Q , respectively, before the most recent

↑ transition of the clock

DS006712

www.fairchildsemi.com

12 3 4 5 6

中文翻译

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与DM74ALS165M_NL相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS165MX	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS165N	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS165N/A+	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,PLASTIC
DM74ALS165N/B+	NSC	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,PLASTIC
DM74ALS165NX	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS166J	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,CERAMIC
DM74ALS166J/A+	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,CERAMIC
DM74ALS166M/A+	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,SOP,16PIN,PLASTIC
DM74ALS166N	TI	获取价格	ALS SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDIP16, PLASTI
DM74ALS166N/A+	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,PLASTIC

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