DM74ALS165

更新时间： 2024-11-03 22:56:47

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		移位寄存器
页数	文件大小	规格书
6页	67K
描述
8-Bit Parallel In/Serial Out Shift Register

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DM74ALS165 数据手册

January 1986

Revised February 2000

DM74ALS165

8-Bit Parallel In/Serial Out Shift Register

General Description

The DM74ALS165 is an 8-bit serial register that, when

Features

■ Complementary outputs

clocked, shifts the data toward serial output, Q_H. Parallel-in

■ Direct overriding load (data) inputs

■ Gated clock inputs

access to each stage is provided by eight individual direct

data inputs that are enabled by a low level at the SH/LD

input. The DM74ALS165 also features a clock inhibit func-

tion and a complemented serial output, Q_H.

■ Parallel-to-serial data conversion

Clocking is accomplished by a LOW-to-HIGH transition of

the CLK input while SH/LD is held HIGH and CLK INH is

held LOW. The functions of the CLK and CLK INH (clock

inhibit) inputs are interchangeable. Since a LOW CLK input

and a LOW-to-HIGH transition of CLK INH will also accom-

plish clocking, CLK INH should be changed to the high

level only while the CLK input is HIGH. Parallel loading is

inhibited when SH/LD is held HIGH. The parallel inputs to

the register are enabled while SH/LD is LOW indepen-

dently of the levels of CLK, CLK INH, or SER inputs.

Ordering Code:

Order Number Package Number

Package Description

DM74ALS165M

DM74ALS165N

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

Internal

Shift/ Clock Clock Serial Parallel Outputs Output

A...H

Q_A

Q_B

Q_H

Load Inhibit

↑

a...h

Q_A0Q_B0

Q_H0

Q_Gn

Q_H0

Q_An

↑

Q_A0Q_B0

H = HIGH Level (steady-state),

L = LOW Level (steady-state)

X = Don't Care (any input, including transitions)

↑ = Transition from LOW-to-HIGH level

a...h = The level of steady-state input at inputs A through H, respectively

, Q , Q = The level of Q , Q , or Q , respectively, before the

B0 H0 A B H

indicated steady-state input conditions were established

, Q = The level of Q or Q , respectively, before the most recent

↑ transition of the clock

DS006712

www.fairchildsemi.com

12 3 4 5 6

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与DM74ALS165相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS165J	NSC	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,CERAMIC
DM74ALS165J/A+	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,CERAMIC
DM74ALS165M	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS165M_NL	FAIRCHILD	获取价格	Parallel In Serial Out, ALS Series, 8-Bit, Right Direction, Complementary Output, TTL, PDS
DM74ALS165MX	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS165N	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS165N/A+	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,PLASTIC
DM74ALS165N/B+	NSC	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,PLASTIC
DM74ALS165NX	FAIRCHILD	获取价格	8-Bit Parallel In/Serial Out Shift Register
DM74ALS166J	TI	获取价格	IC,SHIFT REGISTER,ALS-TTL,DIP,16PIN,CERAMIC

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