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DM74ALS14N PDF预览

DM74ALS14N

更新时间: 2024-11-09 22:56:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 80K
描述
Hex Inverter with Schmitt Trigger Inputs

DM74ALS14N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.61
系列:ALSJESD-30 代码:R-PDIP-T14
JESD-609代码:e3长度:19.18 mm
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
功能数量:6输入次数:1
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE电源:5 V
最大电源电流(ICC):12 mAProp。Delay @ Nom-Sup:12 ns
传播延迟(tpd):12 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:5.08 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
宽度:7.62 mmBase Number Matches:1

DM74ALS14N 数据手册

 浏览型号DM74ALS14N的Datasheet PDF文件第2页浏览型号DM74ALS14N的Datasheet PDF文件第3页浏览型号DM74ALS14N的Datasheet PDF文件第4页浏览型号DM74ALS14N的Datasheet PDF文件第5页浏览型号DM74ALS14N的Datasheet PDF文件第6页 
March 1986  
Revised February 2000  
DM74ALS14  
Hex Inverter with Schmitt Trigger Inputs  
General Description  
Features  
This device contains six independent gates, each of which  
performs the logic INVERT function. Each input has hyster-  
esis which increases the noise immunity and transforms a  
slowly changing input signal to a fast changing, jitter-free  
output.  
Input hysteresis  
Low output noise generation  
High input noise immunity  
Switching specification at 50 pF  
Switching specifications guaranteed over full tempera-  
ture and VCC range  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Functionally and pin-for-pin compatible with Schottky  
and low power Schottky TTL counterparts  
Improved AC performance over low power Schottky  
counterpart  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS14M  
DM74ALS14SJ  
DM74ALS14N  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = A  
Input  
Output  
A
L
Y
H
L
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS008773  
www.fairchildsemi.com  

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