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DM74ALS125N PDF预览

DM74ALS125N

更新时间: 2024-09-20 22:56:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 55K
描述
Quad 3-STATE Buffer

DM74ALS125N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:0.300 INCH, PLASTIC, MS-001, DIP-14
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.21
Is Samacsys:N控制类型:ENABLE LOW
系列:ALSJESD-30 代码:R-PDIP-T14
JESD-609代码:e3长度:19.18 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT APPLICABLE
电源:5 V最大电源电流(ICC):18 mA
Prop。Delay @ Nom-Sup:10 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
宽度:7.62 mmBase Number Matches:1

DM74ALS125N 数据手册

 浏览型号DM74ALS125N的Datasheet PDF文件第2页浏览型号DM74ALS125N的Datasheet PDF文件第3页浏览型号DM74ALS125N的Datasheet PDF文件第4页浏览型号DM74ALS125N的Datasheet PDF文件第5页 
November 1989  
Revised February 2000  
DM74ALS125  
Quad 3-STATE Buffer  
General Description  
Features  
This device contains four independent gates each of which  
performs a non-inverting buffer function. The outputs have  
the 3-STATE feature. The 3-STATE circuitry contains a fea-  
ture that maintains the buffer outputs in 3-STATE (high  
impedance state) during power supply ramp-up or ramp-  
down. This eliminates bus glitching problems that arise  
during power-up and power-down. To minimize the possi-  
bility that two outputs will attempt to take a common bus to  
opposite logic levels, the disable time is shorter than the  
enable time of the outputs.  
Advanced low power oxide-isolated ion-implanted  
Schottky TTL process  
Functional and pin compatible with the 74LS counterpart  
Switching response specified into 500and 50 pF load  
Switching response specifications guaranteed over full  
temperature and VCC supply range  
PNP input design reduces input loading  
Low level drive current: 74ALS = 24 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74ALS125M  
DM74ALS125N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Functional Table  
Y = A  
Input  
Output  
A
L
C
L
Y
L
H
X
L
H
H
Hi-Z  
H = HIGH Logic Level  
L = LOW Logic Level  
X = Either LOW or HIGH Logic Level  
Hi-Z = 3-STATE (Outputs are disabled)  
© 2000 Fairchild Semiconductor Corporation  
DS010620  
www.fairchildsemi.com  

DM74ALS125N 替代型号

型号 品牌 替代类型 描述 数据表
DM74LS125AN FAIRCHILD

类似代替

Quad 3-STATE Buffer
SN74LS125AN TI

功能相似

QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN54LS125AJ TI

功能相似

QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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