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DM74ALS1240AWM PDF预览

DM74ALS1240AWM

更新时间: 2024-09-22 22:07:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
4页 43K
描述
Octal 3-STATE Bus Driver

DM74ALS1240AWM 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP20,.4
针数:20Reach Compliance Code:unknown
风险等级:5.55控制类型:ENABLE LOW
系列:ALSJESD-30 代码:R-PDSO-G20
JESD-609代码:e0长度:12.8 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):14 mA
Prop。Delay @ Nom-Sup:13 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:2.65 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.5 mmBase Number Matches:1

DM74ALS1240AWM 数据手册

 浏览型号DM74ALS1240AWM的Datasheet PDF文件第2页浏览型号DM74ALS1240AWM的Datasheet PDF文件第3页浏览型号DM74ALS1240AWM的Datasheet PDF文件第4页 
September 1986  
Revised February 2000  
DM74ALS1240A  
Octal 3-STATE Bus Driver  
General Description  
Features  
These octal 3-STATE bus drivers are designed to provide  
the designer with flexibility in implementing a bus interface  
with memory, microprocessor, or communication systems,  
and are low power dissipation versions of the  
DM74ALS240A and DM74ALS241A. The output 3-STATE  
gating control is organized into two separate groups of four  
buffers. The DM74ALS1240A control inputs symmetrically  
enable the respective outputs when set logic LOW. The 3-  
STATE circuitry contains a feature that maintains the buffer  
outputs in 3-STATE (high impedance state) during power  
supply ramp-up or ramp-down. This eliminates bus glitch-  
ing problems that arise during power-up and power-down.  
Advanced oxide-isolated, ion-implanted Schottky TTL  
process  
Switching response specified into 500and 50 pF load  
Switching response specifications guaranteed over full  
temperature and VCC supply range  
PNP input design reduces input loading  
Low power dissipation version  
Low level drive current: 74ALS = 16 mA  
Ordering Code:  
Order Number  
Package Number  
Package Description  
DM74ALS1240AWM  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Logic Diagram  
Function Table  
Input  
Output  
G
L
A
L
Y
H
L
L
H
X
H
Z
H = HIGH Level Logic State  
L = LOW Level Logic State  
X = Don't Care (Either LOW or HIGH Level Logic State)  
Z = High Impedance (OFF) State  
© 2000 Fairchild Semiconductor Corporation  
DS006261  
www.fairchildsemi.com  

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