DM74ALS109ANX

更新时间： 2024-09-22 05:20:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
6页	58K
描述
Dual J-K Positive-Edge-Triggered Flip-Flop

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数据手册

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DM74ALS109ANX 数据手册

April 1984

Revised February 2000

DM74ALS109A

Dual J-K Positive-Edge-Triggered Flip-Flop

with Preset and Clear

General Description

The DM74ALS109A is a dual edge-triggered flip-flop. Each

flip-flop has individual J, K, clock, clear and preset inputs,

and also complementary Q and Q outputs.

Features

■ Switching specifications at 50 pF

■ Switching specifications guaranteed over full tempera-

ture and V_CCrange

Information at input J or K is transferred to the Q output on

the positive going edge of the clock pulse. Clock triggering

occurs at a voltage level of the clock pulse and is not

directly related to the transition time of the positive going

pulse. When the clock input is at either the HIGH or LOW

level, the J, K input signal has no effect.

■ Advanced oxide-isolated, ion-implanted Schottky TTL

process

■ Functionally and pin for pin compatible with Schottky

and LS TTL counterpart

■ Improved AC performance over LS109 at approximately

half the power

Asynchronous preset and clear inputs will set or clear Q

output respectively upon the application of low level signal.

The J-K design allows operation as a D flip-flop by tying the

J and K inputs together.

Ordering Code:

Order Number Package Number

Package Description

DM74ALS109AM

DM74ALS109AN

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Inputs

PR CLR CK

Outputs

↑

H (Note 1) H (Note 1)

↑

TOGGLE

↑

Q₀

L = LOW State

H = HIGH State

X = Don't Care

↑ = Positive Edge Transition,

= Previous Condition of Q

Note 1: This condition is nonstable; it will not persist when present and

clear inputs return to their inactive (HIGH) level. The output levels in this

condition are not guaranteed to meet the V

specification.

DS006196

www.fairchildsemi.com

12 3 4 5 6

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与DM74ALS109ANX相关器件

型号	品牌	获取价格	描述	数据表
DM74ALS109J/A+	ETC	获取价格	J-K-Type Flip-Flop
DM74ALS109N	NSC	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,ALS-TTL,DIP,16PIN,PLASTIC
DM74ALS109N/A+	ETC	获取价格	J-K-Type Flip-Flop
DM74ALS109N/B+	ETC	获取价格	J-K-Type Flip-Flop
DM74ALS10A	FAIRCHILD	获取价格	Triple 3-Input NAND Gate
DM74ALS10AJ/A+	ETC	获取价格	Triple 3-input NAND Gate
DM74ALS10AM	FAIRCHILD	获取价格	Triple 3-Input NAND Gate
DM74ALS10AM/A+	ETC	获取价格	Triple 3-input NAND Gate
DM74ALS10AM/B+	ETC	获取价格	Triple 3-input NAND Gate
DM74ALS10AM_NL	FAIRCHILD	获取价格	NAND Gate, ALS Series, 3-Func, 3-Input, TTL, PDSO14, 0.150 INCH, LEAD FREE, MS-012, SOIC-1