DM7476CW

更新时间： 2024-09-25 12:58:27

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		触发器
页数	文件大小	规格书
4页	44K
描述
J-K Flip-Flop, 74 Series, 2-Func, Negative Edge Triggered, 2-Bit, Complementary Output, WAFER

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DM7476CW 技术参数

生命周期：	Obsolete	零件包装代码：	WAFER
包装说明：	,	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.71
系列：	74	JESD-30 代码：	X-XUUC-N
逻辑集成电路类型：	J-K FLIP-FLOP	位数：	2
功能数量：	2	最高工作温度：	70 °C
最低工作温度：		输出极性：	COMPLEMENTARY
封装主体材料：	UNSPECIFIED	封装形状：	UNSPECIFIED
封装形式：	UNCASED CHIP	传播延迟（tpd）：	40 ns
认证状态：	Not Qualified	最大供电电压 (Vsup)：	5.25 V
最小供电电压 (Vsup)：	4.75 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	温度等级：	COMMERCIAL
端子形式：	NO LEAD	端子位置：	UPPER
触发器类型：	NEGATIVE EDGE	最小 fmax：	15 MHz
Base Number Matches：	1

DM7476CW 数据手册

September 1986

Revised February 2000

DM7476

Dual Master-Slave J-K Flip-Flops with

Clear, Preset, and Complementary Outputs

negative transition of the clock, the data from the master is

transferred to the slave. The logic state of J and K inputs

must not be allowed to change while the clock is HIGH.

The data is transferred to the outputs on the falling edge of

the clock pulse. A LOW logic level on the preset or clear

inputs will set or reset the outputs regardless of the logic

levels of the other inputs.

General Description

This device contains two independent positive pulse trig-

gered J-K flip-flops with complementary outputs. The J and

K data is processed by the flip-flop after a complete clock

pulse. While the clock is LOW the slave is isolated from the

master. On the positive transition of the clock, the data

from the J and K inputs is transferred to the master. While

the clock is HIGH the J and K inputs are disabled. On the

Ordering Code:

Order Number Package Number

Package Description

DM7476N

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Connection Diagram

Function Table

Inputs

Outputs

CLR

CLK

(Note 1) (Note 1)

Q₀

Toggle

H = HIGH Logic Level

L = LOW Logic Level

X = Either LOW or HIGH Logic Level

= Positive pulse data. The J and K inputs must be held constant while

the clock is HIGH. Data is transferred to the outputs on the falling

edge of the clock pulse.

= The output logic level before the indicated input conditions were

established.

Toggle = Each output changes to the complement of its previous level on

each complete active HIGH level clock pulse.

Note 1: This configuration is nonstable; that is, it will not persist when the

preset and/or clear inputs return to their inactive (HIGH) level.

DS006528

www.fairchildsemi.com

12 3 4

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与DM7476CW相关器件

型号	品牌	获取价格	描述	数据表
DM7476J	NSC	获取价格	IC,FLIP-FLOP,DUAL,J/K TYPE,STD-TTL,DIP,16PIN,CERAMIC
DM7476J/A+	ETC	获取价格	J-K-Type Flip-Flop
DM7476N	FAIRCHILD	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7476N	NSC	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7476N/A+	ETC	获取价格	J-K-Type Flip-Flop
DM7476N/B+	ETC	获取价格	J-K-Type Flip-Flop
DM7476W	NSC	获取价格	Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs
DM7483J	NSC	获取价格	IC,BINARY ADDER,STD-TTL,DIP,16PIN,CERAMIC
DM7483J/A+	ETC	获取价格	Binary Adder
DM7483N	NSC	获取价格	IC,BINARY ADDER,STD-TTL,DIP,16PIN,PLASTIC

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