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DM7474

更新时间: 2024-09-24 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
5页 55K
描述
Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs

DM7474 数据手册

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September 1986  
Revised February 2000  
DM7474  
Dual Positive-Edge-Triggered D-Type Flip-Flops with  
Preset, Clear and Complementary Outputs  
transition time of the rising edge of the clock. The data on  
the D input may be changed while the clock is LOW or  
General Description  
This device contains two independent positive-edge-trig-  
HIGH without affecting the outputs as long as the data  
gered D-type flip-flops with complementary outputs. The  
setup and hold times are not violated. A LOW logic level on  
information on the D input is accepted by the flip-flops on  
the preset or clear inputs will set or reset the outputs  
the positive going edge of the clock pulse. The triggering  
regardless of the logic levels of the other inputs.  
occurs at a voltage level and is not directly related to the  
Ordering Code:  
Order Number Package Number  
Package Description  
DM7474M  
DM7474N  
M14A  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Outputs  
PR  
L
CLR  
CLK  
X
D
X
X
X
Q
Q
L
H
L
L
H
L
H
X
H
H
L
X
H
(Note 1) (Note 1)  
H
H
H
H
H
H
L
H
L
H
L
L
H
X
Q0  
Q0  
H = HIGH Logic Level  
X = Either LOW or HIGH Logic Level  
L = LOW Logic Level  
↑ = Positive-going transition of the clock.  
Q
= The output logic level of Q before the indicated input conditions were  
0
established.  
Note 1: This configuration is nonstable; that is, it will not persist when either  
the preset and/or clear inputs return to their inactive (HIGH) level.  
© 2000 Fairchild Semiconductor Corporation  
DS006526  
www.fairchildsemi.com  

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