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DM7438M PDF预览

DM7438M

更新时间: 2024-09-24 22:54:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 65K
描述
Quad 2-Input NAND Buffers with Open-Collector Outputs

DM7438M 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.43
系列:TTL/H/LJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:8.65 mm
逻辑集成电路类型:NAND GATE最大I(ol):0.048 A
功能数量:4输入次数:2
端子数量:14最高工作温度:70 °C
最低工作温度:输出特性:OPEN-COLLECTOR
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):54 mA
Prop。Delay @ Nom-Sup:22 ns传播延迟(tpd):22 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

DM7438M 数据手册

 浏览型号DM7438M的Datasheet PDF文件第2页浏览型号DM7438M的Datasheet PDF文件第3页浏览型号DM7438M的Datasheet PDF文件第4页浏览型号DM7438M的Datasheet PDF文件第5页 
September 1986  
Revised February 2000  
DM7438 • 7438  
Quad 2-Input NAND Buffers with Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
This device contains four independent gates each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical  
operation.  
Where:  
N1 (IOH) = total maximum output high current  
for all outputs tied to pull-up resistor  
N2 (IIH) = total maximum input high current for  
all inputs tied to pull-up resistor  
N3 (IIL) = total maximum input low current for  
all inputs tied to pull-up resistor  
Ordering Code:  
Order Number Package Number  
Package Description  
DM7438M  
DM7438N  
7438SJ  
M14A  
N14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Y = AB  
Inputs  
Output  
A
L
B
L
Y
H
H
H
L
L
H
L
H
H
H
H = HIGH Logic Level  
L = LOW Logic Level  
© 2000 Fairchild Semiconductor Corporation  
DS006513  
www.fairchildsemi.com  

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