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DM54LS55J14A

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DM54LS55J14A 数据手册

April 1992

DM54LS55/DM74LS55

2-Wide, 4-Input AND-OR-INVERT Gate

General Description

This device contains a combination of AND-OR-INVERT

functions. The internal gates are configured as two,

four-input AND gates with their outputs connected to a

two-input NOR gate.

Connection Diagram

Dual-In-Line Package

TL/F/10174–1

Order Number DM54LS55J, DM54LS55W, DM74LS55M or DM74LS55N

See NS Package Number J14A, M14A, N14A or W14B

Function Table

ABCD

EFGH

Inputs

Output

All Other Combinations

High Logic Level

Low Logic Level

Either Low or High Logic Level

1995 National Semiconductor Corporation

TL/F/10174

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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型号	品牌	获取价格	描述	数据表
DM54LS55W	NSC	获取价格	2-Wide, 4-Input AND-OR-INVERT Gate
DM54LS55W/883	ROCHESTER	获取价格	AND-OR-Invert Gate
DM54LS55W14B	NSC	获取价格	2-Wide, 4-Input AND-OR-INVERT Gate
DM54LS645J	TI	获取价格	IC,BUS TRANSCEIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,CERAMIC
DM54LS645J/883	TI	获取价格	IC,BUS TRANSCEIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,CERAMIC
DM54LS645J/883B	TI	获取价格	IC,BUS TRANSCEIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,CERAMIC
DM54LS645J/883C	TI	获取价格	IC,BUS TRANSCEIVER,SINGLE,8-BIT,LS-TTL,DIP,20PIN,CERAMIC
DM54LS670	NSC	获取价格	TRI-STATE 4-BY-4 REGISTER FILES
DM54LS670J	ROCHESTER	获取价格	Standard SRAM
DM54LS670J/883	ROCHESTER	获取价格	Standard SRAM, 4X4, 45ns, TTL, CDIP16, CERAMIC, DIP-16