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DM54LS259 PDF预览

DM54LS259

更新时间： 2024-02-14 12:57:02
品牌 Logo 应用领域
美国国家半导体 - NSC 锁存器
页数 文件大小 规格书
6页 156K
描述
8-Bit Addressable Latches

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中文翻译

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DM54LS259 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：CERAMIC, FP-16针数：16
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.75Is Samacsys：N
其他特性：1:8 DMUX FOLLOWED BY LATCH; RESET ACTIVE ONLY WHEN LATCH ENABLE IS HIGH系列：LS
JESD-30 代码：R-GDFP-F16长度：9.6645 mm
逻辑集成电路类型：D LATCH位数：1
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-55 °C
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：27 ns
座面最大高度：2.032 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：TTL
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
触发器类型：LOW LEVEL宽度：6.604 mm
Base Number Matches：1

DM54LS259 数据手册

 浏览型号DM54LS259的Datasheet PDF文件第2页浏览型号DM54LS259的Datasheet PDF文件第3页浏览型号DM54LS259的Datasheet PDF文件第4页浏览型号DM54LS259的Datasheet PDF文件第5页浏览型号DM54LS259的Datasheet PDF文件第6页 
May 1992  
DM54LS259/DM74LS259 8-Bit Addressable Latches  
General Description  
Features  
Y
8-Bit parallel-out storage register performs serial-to-par-  
allel conversion with storage  
Asynchronous parallel clear  
Active high decoder  
These 8-bit addressable latches are designed for general  
purpose storage applications in digital systems. Specific  
uses include working registers, serial-holding registers, and  
active-high decoders or demultiplexers. They are multifunc-  
tional devices capable of storing single-line data in eight  
addressable latches, and being a 1-of-8 decoder or demulti-  
plexer with active-high outputs.  
Y
Y
Y
Y
Y
Y
Y
Enable/disable input simplifies expansion  
Direct replacement for Fairchild 9334  
Expandable for N-bit applications  
Four distinct functional modes  
Typical propagation delay times:  
Enable-to-output 18 ns  
Four distinct modes of operation are selectable by control-  
ling the clear and enable inputs as enumerated in the func-  
tion table. In the addressable-latch mode, data at the data-  
in terminal is written into the addressed latch. The ad-  
dressed latch will follow the data input with all unaddressed  
latches remaining in their previous states. In the memory  
mode, all latches remain in their previous states and are  
unaffected by the data or address inputs. To eliminate the  
possibility of entering erroneous data in the latches, the en-  
able should be held high (inactive) while the address lines  
are changing. In the 1-of-8 decoding or demultiplexing  
mode, the addressed output will follow the level of the D  
input with all other outputs low. In the clear mode, all out-  
puts are low and unaffected by the address and data inputs.  
Data-to-output 16 ns  
Address-to-output 21 ns  
Clear-to-output 17 ns  
Y
Fan-out  
I
(sink current)  
OL  
54LS259 4 mA  
74LS259 8 mA  
(source current) 0.4 mA  
b
I
OH  
Y
Typical I  
22 mA  
CC  
Connection Diagram  
Function Table  
Inputs  
Output of Each  
Addressed Other  
Dual-In-Line Package  
Function  
Latch  
Output  
Clear  
E
H
H
L
L
H
L
D
Q
Q
L
Addressable Latch  
Memory  
8-Line Demultiplexer  
Clear  
i0  
Q
i0  
i0  
D
L
L
H
L
Latch Selection Table  
Select Inputs  
B
Latch  
Addressed  
C
A
L
L
L
L
L
H
H
L
L
H
L
H
L
0
1
2
3
4
5
6
7
L
H
H
H
H
L
H
H
H
L
H
TL/F/6418–1  
Order Number DM54LS259E, DM54LS259J,  
DM54LS259W, DM74LS259M,  
DM74LS259WM or DM74LS259N  
See NS Package Number E20A, J16A,  
M16A, M16B, N16E or W16A  
e
e
e
Low Level  
H
D
Q
High Level, L  
the Level of the Data Input  
e
e
0, 1, . . . 7, as Appropriate) before the Indicated  
the Level of Q (i  
i
i0  
Steady-State Input Conditions Were Established.  
C
1995 National Semiconductor Corporation  
TL/F/6418  
RRD-B30M105/Printed in U. S. A.  
123456

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