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DM54LS241W PDF预览

DM54LS241W

更新时间: 2024-11-23 22:56:47
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器逻辑集成电路输出元件
页数 文件大小 规格书
6页 145K
描述
Octal TRI-STATE Buffers/Line Drivers/Line Receivers

DM54LS241W 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:DFP, LCC20,.35SQReach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.23Is Samacsys:N
其他特性:OUTPUT ENABLE ACTIVE HIGH FOR ONE FUNCTION控制类型:ENABLE LOW/HIGH
系列:LSJESD-30 代码:R-GDFP-F20
JESD-609代码:e0逻辑集成电路类型:BUS DRIVER
最大I(ol):0.012 A位数:8
功能数量:2端口数量:2
端子数量:20最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:LCC20,.35SQ
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):54 mAProp。Delay @ Nom-Sup:18 ns
传播延迟(tpd):18 ns认证状态:Not Qualified
座面最大高度:2.286 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.731 mm
Base Number Matches:1

DM54LS241W 数据手册

 浏览型号DM54LS241W的Datasheet PDF文件第2页浏览型号DM54LS241W的Datasheet PDF文件第3页浏览型号DM54LS241W的Datasheet PDF文件第4页浏览型号DM54LS241W的Datasheet PDF文件第5页浏览型号DM54LS241W的Datasheet PDF文件第6页 
April 1992  
DM54LS240/DM74LS240,  
DM54LS241/DM74LS241  
Octal TRI-STATE Buffers/Line Drivers/Line Receivers  
Y
É
Typical I (sink current)  
OL  
General Description  
54LS  
74LS  
12 mA  
24 mA  
These buffers/line drivers are designed to improve both the  
performance and PC board density of TRI-STATE buffers/  
drivers employed as memory-address drivers, clock drivers,  
and bus-oriented transmitters/receivers. Featuring 400 mV  
of hysteresis at each low current PNP data line input, they  
provide improved noise rejection and high fanout outputs  
and can be used to drive terminated lines down to 133X.  
Y
Y
Typical I  
54LS  
74LS  
(source current)  
OH  
b
b
12 mA  
15 mA  
Typical propagation delay times  
Inverting 10.5 ns  
Noninverting 12 ns  
Y
Y
Typical enable/disable time 18 ns  
Typical power dissipation (enabled)  
Features  
Y
TRI-STATE outputs drive bus lines directly  
Inverting 130 mW  
Noninverting 135 mW  
Y
PNP inputs reduce DC loading on bus lines  
Y
Hysteresis at data inputs improves noise margins  
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/F/6411–1  
TL/F/6411–2  
Order Number DM54LS240J,  
DM54LS240W, DM54LS240E,  
DM74LS240WM or DM74LS240N  
See NS Package Number E20A, J20A,  
M20B, N20A or W20A  
Order Number DM54LS241J,  
DM54LS241W, DM54LS241E,  
DM74LS241WM or DM74LS241N  
See NS Package Number E20A, J20A,  
M20B, N20A or W20A  
Function Tables  
LS240  
LS241  
G
Inputs  
Output  
Y
Inputs  
1A  
Outputs  
G
A
G
2A  
1Y  
2Y  
L
L
L
H
X
H
L
X
X
X
H
H
L
L
L
L
H
X
X
X
X
X
X
X
L
L
H
Z
H
Z
H
X
X
X
L
H
Z
H
X
e
e
e
e
L
Low Logic Level  
High Logic Level  
H
X
Z
Either Low or High Logic Level  
High Impedance  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6411  
RRD-B30M105/Printed in U. S. A.  

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