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DM54LS03 PDF预览

DM54LS03

更新时间: 2024-09-27 22:56:47
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
7页 130K
描述
Quad 2-Input NAND Gates with Open-Collector Outputs

DM54LS03 数据手册

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June 1989  
54LS03/DM54LS03/DM74LS03  
Quad 2-Input NAND Gates  
with Open-Collector Outputs  
General Description  
This device contains four independent gates each of which  
performs the logic NAND function. The open-collector out-  
puts require external pull-up resistors for proper logical op-  
eration.  
Pull-Up Resistor Equations  
b
V
(Min)  
V
CC  
(I  
OH  
(I  
e
R
MAX  
a
N
1
)
OH  
N
)
2
IH  
b
V
OL  
V
(Max)  
CC  
e
R
MIN  
b
I
N
(I )  
IL  
OL  
3
Features  
Y
e
outputs tied to pull-up resistor  
Where: N (I  
1
)
OH  
total maximum output high current for all  
Alternate Military/Aerospace device (54LS03) is avail-  
able. Contact a National Semiconductor Sales Office/  
Distributor for specifications.  
e
inputs tied to pull-up resistor  
N
(I  
)
IH  
total maximum input high current for all  
2
e
inputs tied to pull-up resistor  
N
(I  
IL  
)
total maximum input low current for all  
3
Connection Diagram  
Dual-In-Line Package  
TL/F/6344–1  
Order Number 54LS03DMQB, 54LS03FMQB, 54LS03LMQB,  
DM54LS03J, DM54LS03W, DM74LS03M or DM74LS03N  
See NS Package Number E20A, J14A, M14A, N14A or W14B  
Function Table  
e
Y
AB  
Inputs  
Output  
Y
A
B
L
L
L
H
L
H
H
H
L
H
H
H
e
e
H
L
High Logic Level  
Low Logic Level  
C
1995 National Semiconductor Corporation  
TL/F/6344  
RRD-B30M105/Printed in U. S. A.  

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