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DM54367W PDF预览

DM54367W

更新时间: 2024-10-26 22:51:39
品牌 Logo 应用领域
美国国家半导体 - NSC 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
4页 97K
描述
Hex TRI-STATE Buffers

DM54367W 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:CERAMIC, FP-16Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.39.00.01
风险等级:5.52Is Samacsys:N
其他特性:ONE FUNCTION WITH TWO BITS控制类型:ENABLE LOW
系列:TTL/H/LJESD-30 代码:R-GDFP-F16
JESD-609代码:e0长度:9.6645 mm
逻辑集成电路类型:BUS DRIVER最大I(ol):0.032 A
位数:4功能数量:2
端口数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL16,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):85 mA
Prop。Delay @ Nom-Sup:22 ns传播延迟(tpd):22 ns
认证状态:Not Qualified座面最大高度:2.032 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.604 mmBase Number Matches:1

DM54367W 数据手册

 浏览型号DM54367W的Datasheet PDF文件第2页浏览型号DM54367W的Datasheet PDF文件第3页浏览型号DM54367W的Datasheet PDF文件第4页 
June 1989  
DM54367 Hex TRI-STATE Buffers  
É
General Description  
This device contains six independent gates each of which  
performs a non-inverting buffer function. The outputs have  
the TRI-STATE feature. When enabled, the outputs exhibit  
the low impedance characteristics of a standard TTL output  
with additional drive capability to permit the driving of bus  
lines without external resistors. When disabled, both the  
output transistors are turned off presenting a high-imped-  
ance state to the bus line. Thus the output will act neither as  
a signficant load nor as a driver. To minimize the possibility  
that two outputs will attempt to take a common bus to oppo-  
site logic levels, the disable time is shorter than the enable  
time of the outputs.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6572–1  
Order Number DM54367J or DM54367W  
See NS Package Number J16A or W16A  
Function Table  
e
Y
A
Input  
Output  
Y
G
A
L
L
L
H
X
L
H
H
Hi-Z  
e
e
e
H
L
High Logic Level  
Low Logic Level  
X
Either Low or High Logic Level  
e
Hi-Z  
TRI-STATE (Outputs are disabled)  
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/6572  
RRD-B30M105/Printed in U. S. A.  

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