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DM5420W-MLS PDF预览

DM5420W-MLS

更新时间: 2024-11-18 13:07:23
品牌 Logo 应用领域
美国国家半导体 - NSC 栅极触发器逻辑集成电路
页数 文件大小 规格书
4页 96K
描述
IC TTL/H/L SERIES, DUAL 4-INPUT NAND GATE, CDFP14, CERPACK-14, Gate

DM5420W-MLS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
包装说明:CERPACK-14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N系列:TTL/H/L
JESD-30 代码:R-GDFP-F14JESD-609代码:e0
负载电容(CL):15 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.016 A功能数量:2
输入次数:4端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL14,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):11 mA
Prop。Delay @ Nom-Sup:22 ns传播延迟(tpd):15 ns
认证状态:Not Qualified施密特触发器:NO
筛选级别:38535Q/M;38534H;883B座面最大高度:2.032 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.2865 mmBase Number Matches:1

DM5420W-MLS 数据手册

 浏览型号DM5420W-MLS的Datasheet PDF文件第2页浏览型号DM5420W-MLS的Datasheet PDF文件第3页浏览型号DM5420W-MLS的Datasheet PDF文件第4页 
June 1989  
5420/DM5420/DM7420  
Dual 4-Input NAND Gates  
General Description  
This device contains two independent gates each of which  
performs the logic NAND function.  
Features  
Y
Alternate Military/Aerospace device (5420) is available.  
Contact a National Semiconductor Sales Office/Distrib-  
utor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6506–1  
Order Number 5420DMQB, 5420FMQB, DM5420J, DM5420W or DM7420N  
See NS Package Number J14A, N14A or W14B  
Function Table  
e
Y
ABCD  
D
Inputs  
Output  
Y
A
B
C
X
X
X
L
X
X
L
X
L
L
X
X
X
H
H
H
H
H
L
X
X
H
X
H
H
e
e
e
H
L
High Logic Level  
Low Logic Level  
X
Either Low or High Logic Level  
C
1995 National Semiconductor Corporation  
TL/F/6506  
RRD-B30M105/Printed in U. S. A.  

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