Datasheet > DM54180W

DM54180W

更新时间： 2024-11-16 23:47:15

品牌	Logo	应用领域
其他 - ETC		逻辑集成电路
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6页	106K
描述
Parity Generator/Checker

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数据手册

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DM54180W 数据手册

June 1989

DM54180/DM74180 9-Bit Parity Generators/Checkers

General Description

These universal 9-bit (8 data bits plus 1 parity bit) parity

generators/checkers feature odd/even outputs and control

inputs to facilitate operation in either odd or even parity ap-

plications. Depending on whether even or odd parity is be-

ing generated or checked, the even or odd input can be

utilized as the parity or 9th-bit input. The word-length capa-

bility is easily expanded by cascading.

Input buffers are provided so that each data input repre-

sents only one normalized series 54/74 load. A full fan-out

to 10 normalized series 54/74 loads is available from each

of the outputs at a low logic level. A fan-out to 20 normal-

ized loads is provided at a high logic level to facilitate the

connection of unused inputs to used inputs.

Connection Diagram

Dual-In-Line Package

TL/F/6559–1

Order Number DM54180J, DM54180W or DM74180N

See NS Package Number J14A, N14A or W14B

Function Table

Inputs

Outputs

R of H’s at

Even

Odd

A thru H

Even

Odd

Even

Odd

Even

Odd

Low Level, X Don’t Care

High Level, L

1995 National Semiconductor Corporation

TL/F/6559

RRD-B30M105/Printed in U. S. A.

12 3 4 5 6

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与DM54180W相关器件

型号	品牌	获取价格	描述	数据表
DM54180W/883	NSC	获取价格	IC TTL/H/L SERIES, 8-BIT PARITY GENERATOR/CHECKER, COMPLEMENTARY OUTPUT, CDFP14, CERAMIC,
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DM54180W/883B	TI	获取价格	IC,PARITY GENERATOR/CHECKER,STD-TTL,FP,14PIN,CERAMIC
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