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DM54175W PDF预览

DM54175W

更新时间: 2024-10-25 22:54:35
品牌 Logo 应用领域
美国国家半导体 - NSC 触发器
页数 文件大小 规格书
8页 152K
描述
Hex/Quad D Flip-Flops with Clear

DM54175W 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL16,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:8.57
系列:TTL/H/LJESD-30 代码:R-GDFP-F16
JESD-609代码:e0长度:9.6645 mm
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:30000000 Hz
最大I(ol):0.016 A位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DFP封装等效代码:FL16,.3
封装形状:RECTANGULAR封装形式:FLATPACK
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
最大电源电流(ICC):45 mA传播延迟(tpd):25 ns
认证状态:Not Qualified座面最大高度:2.032 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:FLAT端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.604 mm
最小 fmax:40 MHz

DM54175W 数据手册

 浏览型号DM54175W的Datasheet PDF文件第2页浏览型号DM54175W的Datasheet PDF文件第3页浏览型号DM54175W的Datasheet PDF文件第4页浏览型号DM54175W的Datasheet PDF文件第5页浏览型号DM54175W的Datasheet PDF文件第6页浏览型号DM54175W的Datasheet PDF文件第7页 
June 1989  
54174/DM54174/DM74174, 54175/DM54175/DM74175  
Hex/Quad D Flip-Flops with Clear  
General Description  
Features  
Y
Y
Y
Y
Y
174 contains six flip-flops with single-rail outputs  
175 contains four flip-flops with double-rail outputs  
Buffered clock and direct clear inputs  
Individual data input to each flip-flop  
Applications include:  
These positive-edge triggered flip-flops utilize TTL circuitry  
to implement D-type flip-flop logic. All have a direct clear  
input, and the quad (175) version features complementary  
outputs from each flip-flop.  
Information at the D inputs meeting the setup and hold time  
requirements is transferred to the Q outputs on the positive-  
going edge of the clock pulse. Clock triggering occurs at a  
particular voltage level and is not directly related to the tran-  
sition time of the positive-going pulse. When the clock input  
is at either the high or low level, the D input signal has no  
effect at the output.  
Buffer/storage registers  
Shift registers  
Pattern generators  
Y
Y
Y
Typical clock frequency 40 MHz  
Typical power dissipation per flip-flop 38 mW  
Alternate Military/Aerospace device (54174, 54175) is  
available. Contact a National Semiconductor Sales Of-  
fice/Distributor for specifications.  
Connection Diagrams  
Dual-In-Line Package  
Dual-In-Line Package  
TL/F/6557–2  
Order Number 54175DMQB, 54175FMQB, DM54175J,  
DM54175W or DM74175N  
TL/F/6557–1  
Order Number 54174DMQB, 54174FMQB, DM54174J,  
DM54174W or DM74174N  
See NS Package Number J16A, N16E or W16A  
See NS Package Number J16A, N16E or W16A  
Function Table (Each Flip-Flop)  
Inputs  
Outputs  
²
Q
Clear  
Clock  
D
Q
L
H
H
H
X
u
u
L
X
H
L
L
H
L
H
L
H
X
Q
Q
0
0
e
e
e
H
L
High Level (steady state)  
Low Level (steady state)  
Don’t Care  
X
e
Transition from low to high level  
u
0
e
Q
The level of Q before the indicated steady-state input conditions were established.  
175 only  
e
²
C
1995 National Semiconductor Corporation  
TL/F/6557  
RRD-B30M105/Printed in U. S. A.  

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