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DM5410W PDF预览

DM5410W

更新时间: 2024-11-13 22:29:43
品牌 Logo 应用领域
美国国家半导体 - NSC
页数 文件大小 规格书
4页 96K
描述
Triple 3-Input NAND Gates

DM5410W 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DFP, FL14,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.65
系列:TTL/H/LJESD-30 代码:R-GDFP-F14
JESD-609代码:e0逻辑集成电路类型:NAND GATE
最大I(ol):0.016 A功能数量:3
输入次数:3端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DFP
封装等效代码:FL14,.3封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V最大电源电流(ICC):16.5 mA
Prop。Delay @ Nom-Sup:22 ns传播延迟(tpd):15 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:2.032 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:FLAT
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6.2865 mm
Base Number Matches:1

DM5410W 数据手册

 浏览型号DM5410W的Datasheet PDF文件第2页浏览型号DM5410W的Datasheet PDF文件第3页浏览型号DM5410W的Datasheet PDF文件第4页 
June 1989  
5410/DM5410/DM7410  
Triple 3-Input NAND Gates  
General Description  
This device contains three independent gates each of which  
performs the logic NAND function.  
Features  
Y
Alternate Military/Aerospace device (5410) is available.  
Contact a National Semiconductor Sales Office/Distrib-  
utor for specifications.  
Connection Diagram  
Dual-In-Line Package  
TL/F/6500–1  
Order Number 5410DMQB, 5410FMQB, DM5410J, DM5410W or DM7410N  
See NS Package Number J14A, N14A or W14B  
Function Table  
e
Y
ABC  
C
Inputs  
B
Output  
Y
A
X
X
L
X
L
L
X
X
H
H
H
H
L
X
H
H
e
e
e
H
L
High Logic Level  
Low Logic Level  
X
Either Low or High Logic Level  
C
1995 National Semiconductor Corporation  
TL/F/6500  
RRD-B30M105/Printed in U. S. A.  

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