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DM5406J-MLS PDF预览

DM5406J-MLS

更新时间: 2024-11-14 13:07:23
品牌 Logo 应用领域
美国国家半导体 - NSC /
页数 文件大小 规格书
4页 109K
描述
IC,LOGIC GATE,HEX INVERTER,STD-TTL,DIP,14PIN,CERAMIC

DM5406J-MLS 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP14,.3Reach Compliance Code:not_compliant
风险等级:5.92JESD-30 代码:R-XDIP-T14
JESD-609代码:e0负载电容(CL):15 pF
逻辑集成电路类型:INVERTER最大I(ol):0.03 A
湿度敏感等级:1端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-COLLECTOR封装主体材料:CERAMIC
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:5 V最大电源电流(ICC):51 mA
Prop。Delay @ Nom-Sup:23 ns认证状态:Not Qualified
施密特触发器:NO筛选级别:38535Q/M;38534H;883B
子类别:Gates标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:MILITARY端子面层:Tin/Lead (Sn63Pb37)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUALBase Number Matches:1

DM5406J-MLS 数据手册

 浏览型号DM5406J-MLS的Datasheet PDF文件第2页浏览型号DM5406J-MLS的Datasheet PDF文件第3页浏览型号DM5406J-MLS的Datasheet PDF文件第4页 
June 1989  
DM5406/DM7406 Hex Inverting Buffers with  
High Voltage Open-Collector Outputs  
General Description  
Pull-Up Resistor Equations  
b
This device contains six independent buffers each of which  
performs the logic INVERT function. The open-collector out-  
puts require external pull-up resistors for proper logical op-  
eration.  
V
O
(Min)  
V
OH  
e
R
MAX  
a
N
1
(I  
OH  
)
N
2
(I  
IH  
)
b
V
(Max)  
V
IL  
O
OL  
e
R
MIN  
b
I
N
(I  
)
OL  
3
e
)
OH  
Where: N (I  
total maximum output high current for all  
outputs tied to pull-up resistor  
1
e
)
IH  
N
(I  
total maximum input high current for all  
2
inputs tied to pull-up resistor  
e
inputs tied to pull-up resistor  
N
(I  
IL  
)
total maximum input low current for all  
3
Connection Diagram  
Dual-In-Line Package  
TL/F/6496–1  
Order Number DM5406J, DM5406W, DM7406M or DM7406N  
See NS Package Number J14A, M14A, N14A or W14B  
Function Table  
e
Y
A
Input  
A
Output  
Y
L
H
L
H
e
e
H
L
High Logic Level  
Low Logic Level  
C
1995 National Semiconductor Corporation  
TL/F/6496  
RRD-B30M105/Printed in U. S. A.  

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