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DLPA200

更新时间： 2024-02-16 21:47:18
品牌 Logo 应用领域
德州仪器 - TI 驱动
页数 文件大小 规格书
20页 271K
描述
DLP® DLPA200 DMD Micromirror Driver

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DLPA200 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：TFQFP,
针数：80Reach Compliance Code：unknown
风险等级：5.66Is Samacsys：N
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：S-PQFP-G80
长度：12 mm功能数量：1
端子数量：80最高工作温度：75 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
认证状态：Not Qualified座面最大高度：1.2 mm
最大供电电压：13.2 V最小供电电压：10.8 V
标称供电电压：12 V表面贴装：YES
温度等级：COMMERCIAL EXTENDED端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
Base Number Matches：1

DLPA200 数据手册

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DLPA200  
www.ti.com  
DLPS015A –APRIL 2010–REVISED JUNE 2010  
®
DLP DLPA200 DMD Micromirror Driver  
Check for Samples: DLPA200  
1
FEATURES  
ETQFP PACKAGE  
(TOP VIEW)  
2
•
Designed for use as a part of a DLP Chipset  
•
Generates the Micromirror Clocking Pulses  
required by the DLP Digital Micromirror Device  
(DMD)  
•
Generates specialized voltage levels required  
for micromirror clocking pulse generation  
•
•
Operates from a single 12-V power supply  
GND  
1
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
GND  
2
RESETZ  
SCPENZ  
SCPDI  
SCPCK  
GND  
MODE1  
MODE0  
SEL1  
3
Provides a VBIAS voltage level, used by the  
DMD to control the array border mirrors  
4
5
SEL0  
OEZ  
GND  
6
7
NC  
G
•
•
•
Provides a VOFFSET voltage level, used by the  
DMD as DMDVCC2  
VBIAS_SWL  
VBIAS  
VBIAS_LHI  
P12V  
8
9
NC  
NC  
P12V  
VOFFSET  
P12V  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
All logic inputs are LVTTL and CMOS  
compatible  
VRESET_SWL  
VRESET  
GND  
V5REG  
GND  
DEV_ID1  
STROBE  
A3  
A2  
Packaged in an Pb-free Thermally Enhanced  
Surface-Mount Package: 80-pin, 0.5 mm-pitch,  
enlarged terminal pitch, thin profile quad flat  
pack (eTQFP)  
DEV_ID0  
IRQZ  
A1  
A0  
SCPDO  
GND  
GND  
DESCRIPTION  
The DLPA200 is designed to be used as a part of a complete DLP chipset. A DLP chipset typically consists of a  
DMD, a DMD Controller, DMD Controller Firmware, and the DMD Micromirror Driver.  
Within a chipset, the DLPR200 is responsible for generating micromirror clocking pulses. These clocking pulses  
(also referred to as micromirror reset pulses) are what cause the DMD micromirrors to switch from one binary  
landed state to another (as dictated by the binary contents of the DMD CMOS memory array).  
A DMD Controller is responsible for writing data to the DMD CMOS memory array, and then commanding the  
DLPR200 to generate the required micromirror clocking pulses.  
The DLPA200 consists of three functional blocks: A High-Voltage Power Supply function, a DMD Micromirror  
Clock Generation function, and a Serial Communication function.  
The High-Voltage Power Supply function generates three specialized voltage levels: VBIAS (19 to 28 V), VRESET  
(–19 to –28 V), and VOFFSET (4.5 to 10 V).  
The Micromirror Clock Generation function uses the three voltages generated by the High-Voltage Power Supply  
function to create the sixteen micromirror clock pluses (output the OUTx pins of the DLPA200).  
The Serial Communication function allows the chipset Controller to: control the generation of VBIAS, VRESET, and  
VOFFSET; control the generation of the micromirror clock pulses; status the general operation of the DLPA200.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
DLP is a registered trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010, Texas Instruments Incorporated  
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