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DG642DY PDF预览

DG642DY

更新时间: 2024-10-29 22:29:35
品牌 Logo 应用领域
威世 - VISHAY 复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
10页 103K
描述
Low On-Resistance Wideband/Video Switches

DG642DY 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:unknown风险等级:5.58
Is Samacsys:N模拟集成电路 - 其他类型:DPST
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
正常位置:NO/NC功能数量:1
端子数量:8最大通态电阻 (Ron):9 Ω
最高工作温度:85 °C最低工作温度:-40 °C
输出:SEPARATE OUTPUT封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:15,-3 V认证状态:Not Qualified
子类别:Multiplexer or Switches表面贴装:YES
最长接通时间:100 ns切换:BREAK-BEFORE-MAKE
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

DG642DY 数据手册

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DG641/642/643  
Vishay Siliconix  
Low On-Resistance Wideband/Video Switches  
FEATURES  
BENEFITS  
APPLICATIONS  
D Wide Bandwidth: 500 MHz  
D Low Crosstalk at 5 MHz: –85 dB  
D Low rDS(on): 5 W, DG642  
D TTL Logic Compatible  
D High Precision  
D RF and Video Switching  
D RGB Switching  
D Improved Frequency Response  
D Low Insertion Loss  
D Video Routing  
D Improved System Performance  
D Reduced Board Space  
D Low Power Consumption  
D Cellular Communications  
D ATE  
D Fast Switching: tON 50 ns  
D Single Supply Compatibility  
D High Current: 100 mA, DG642  
D Radar/FLIR Systems  
D Satellite Receivers  
D Programmable Filters  
DESCRIPTION  
The DG641/642/643 are high performance monolithic video  
switches designed for switching wide bandwidth analog and  
digital signals. DG641 is a quad SPST, DG642 is a single  
SPDT, and DG643 is a dual SPDT function. These devices  
have exceptionally low on-resistances (5 W typ—DG642), low  
capacitance and high current handling capability.  
To achieve TTL compatibility, low channel capacitances and  
fast switching times, the DG641/642/643 are built on the  
Vishay Siliconix proprietary D/CMOS process. Each switch  
conducts equally well in both directions when on, and blocks  
up to 14 Vp-p when off. An epitaxial layer prevents latchup.  
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION  
Dual-In-Line and SOIC  
Dual-In-Line and SOIC  
IN  
D
IN  
D
IN  
D
IN  
D
1
2
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
1
1
1
2
1
2
Dual-In-Line and SOIC  
2
GND  
GND  
S
S
2
S
D
IN  
1
1
2
3
4
8
7
6
5
S
1
S
2
V–  
V+  
V+  
1
DG641  
V–  
V+  
GND  
GND  
V–  
D
2
2
S
4
S
3
S
4
S
3
GND  
S
DG642  
GND  
GND  
D
D
4
3
Top View  
D
4
D
3
IN  
4
IN  
3
DG643  
Top View  
Top View  
TRUTH TABLEĊDG641  
TRUTH TABLEĊDG642  
TRUTH TABLEĊDG643  
Logic  
Switch  
Logic  
SW1  
SW2  
Logic SW1, SW2  
SW3, SW4  
0
OFF  
0
OFF  
ON  
0
1
OFF  
ON  
ON  
1
ON  
1
ON  
OFF  
OFF  
Logic “0” v 0.8 V  
Logic “0” v 0.8 V  
Logic “1” w 2.4 V  
Logic “0” v 0.8 V  
Logic “1” w 2.4 V  
Logic “1” w 2.4 V  
Document Number: 70058  
S-52433—Rev. E, 06-Sep-99  
www.vishay.com S FaxBack 408-970-5600  
4-1  

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