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DG542AP PDF预览

DG542AP

更新时间: 2024-11-07 22:36:39
品牌 Logo 应用领域
TEMIC 开关输出元件
页数 文件大小 规格书
10页 156K
描述
Wideband/Video “T” Switches

DG542AP 技术参数

生命周期:TransferredReach Compliance Code:unknown
风险等级:5.69模拟集成电路 - 其他类型:AUDIO/VIDEO SWITCH
JESD-30 代码:R-PDIP-T14标称负供电电压 (Vsup):-3 V
信道数量:2功能数量:2
端子数量:14标称断态隔离度:75 dB
通态电阻匹配规范:2 Ω最大通态电阻 (Ron):60 Ω
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:IN-LINE认证状态:Not Qualified
最大供电电流 (Isup):9 mA标称供电电压 (Vsup):15 V
表面贴装:NO最长断开时间:60 ns
最长接通时间:100 ns技术:NMOS
温度等级:MILITARY端子形式:THROUGH-HOLE
端子位置:DUALBase Number Matches:1

DG542AP 数据手册

 浏览型号DG542AP的Datasheet PDF文件第2页浏览型号DG542AP的Datasheet PDF文件第3页浏览型号DG542AP的Datasheet PDF文件第4页浏览型号DG542AP的Datasheet PDF文件第5页浏览型号DG542AP的Datasheet PDF文件第6页浏览型号DG542AP的Datasheet PDF文件第7页 
DG540/541/542  
Wideband/Video “T” Switches  
Features  
Benefits  
Applications  
D Wide Bandwidth: 500 MHz  
D Flat Frequency Response  
D RF and Video Switching  
D Low Crosstalk: –85 dB  
D High Color Fidelity  
D RGB Switching  
D High Off-Isolation: –80 dB @ 5 MHz D Low Insertion Loss  
D Local and Wide Area Networks  
D Video Routing  
D “T” Switch Configuration  
D TTL Logic Compatible  
D Fast Switching—tON: 45 ns  
D Low rDS(on): 30 W  
D Improved System Performance  
D Reduced Board Space  
D Fast Data Acquisition  
D ATE  
D Reduced Power Consumption  
D Improved Data Throughput  
D Radar/FLR Systems  
D Video Multiplexing  
Description  
The DG540/541/542 are high performance monolithic To achieve TTL compatibility, low channel capacitances  
wideband/video switches designed for switching RF, video and fast switching times, the DG540 family is built on the  
and digital signals. By utilizing a “T” switch configuration Siliconix proprietary D/CMOS process. Each switch  
on each channel, these devices achieve exceptionally low conducts equally well in both directions when on.  
crosstalk and high off-isolation. The crosstalk and  
off-isolation of the DG540 are further improved by the  
introduction of extra GND pins between signal pins.  
Functional Block Diagrams and Pin Configurations  
DG540  
Dual-In-Line  
DG540  
PLCC  
IN  
D
IN  
D
1
2
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
1
1
2
2
3
2
1 20 19  
Truth Table  
GND  
GND  
3
Logic  
Switch  
4
5
6
7
8
18  
17  
16  
15  
14  
S
GND  
1
S
S
2
4
1
V–  
S
2
0
1
OFF  
ON  
V–  
V+  
5
GND  
V+  
GND  
GND  
6
S
4
GND  
Logic “0” v 0.8 V  
Logic “1” w 2 V  
GND  
S
3
S
S
3
7
4
GND  
GND  
8
9
10 11 12 13  
Top View  
D
D
9
4
3
IN  
IN  
10  
4
3
Top View  
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70055.  
Siliconix  
1
S-53694—Rev. E, 28-May-97  

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